ADE7816 datasheet(32/48 Pages) AD

32 / 48 page

ADE7816

Data Sheet

Rev. 0 | Page 32 of 48

I2C Read Operation

The read operation, using the I2C interface of the ADE7816, is

accomplished in two stages. The first stage sets the pointer to

the address of the register; the second stage reads the contents

of the register (see Figure 40).

The first stage is initiated when the master generates a start con-

dition. It consists of one byte, representing the address of the

ADE7816, followed by the 16-bit address of the target register. The

ADE7816 acknowledges every byte received. The address byte is

similar to the address byte of a write operation and is equal to 0x70

(see the I2C Write Operation section for details). After the last

byte of the register address is sent and acknowledged by the

ADE7816, the second stage begins with the master generating

a new start condition, followed by an address byte. The most

significant seven bits of this address byte constitute the address of

the ADE7816, which is 0111000b. Bit 0 of the address byte is a

read/write bit. Because this is a read operation, it must be set to 1;

therefore, the first byte of the read operation is 0x71. After this byte

is received, the

generates an acknowledge. Then the

sends the value of the register, and, after every eight bits

are received, the master generates an acknowledge. All the bytes

are sent with the most significant bit first. Registers can be 8, 16,

or 32 bits. After the last bit of the register is received, the master

does not acknowledge the transfer but, instead, generates a stop

condition.

ADE7816

SPI-Compatible Interface

The ADE7816 SPI is always a slave of the communication and

consists of four pins (with dual functions): SCLK/SCL, MOSI/SDA,

MISO/HSD, and SS/HSA. The functions used in the SPI-compatible

interface are SCLK, MOSI, MISO, and SS. The serial clock for

a data transfer is applied at the SCLK logic input. This logic input

has a Schmitt trigger input structure that allows the use of slow

rising (and falling) clock edges. All data transfer operations

synchronize to the serial clock. Data shifts into the

at the MOSI logic input on the falling edge of SCLK, and the

samples it on the rising edge of SCLK. Data shifts out

of the

at the MISO logic output on a falling edge of SCLK

and can be sampled by the master device on the raising edge of

SCLK. The most significant bit of the word is shifted in and out

first. The maximum serial clock frequency that is supported by

this interface is 2.5 MHz. MISO stays in high impedance when no

data is transmitted from the

shows details of

the connection between the

SPI and a master device

containing a SPI interface.

ADE7816

ADE7816 Figure 38

ADE7816

MOSI/SDA

MISO/HSD

SCLK/SCL

ADE7816

MOSI

MISO

SCK

SPI DEVICE

SS/HSA

Figure 38. Connecting the ADE7816 SPI with a SPI Device

ACKNOWLEDGE

GENERATED BY

ADE7816

SLAVE ADDRESS

MS 8 BITS OF

LS 8 BITS OF

BYTE 3 (MS)

OF REGISTER

BYTE 2 OF REGISTER

BYTE 1 OF REGISTER

BYTE 0 (LS) OF

11 100 00

Figure 39. I2C Write Operation of a 32-Bit Register

ACKNOWLEDGE

GENERATED BY

ADE7816

ACKNOWLEDGE

GENERATED BY

MASTER

SLAVE ADDRESS

MSB 8 BITS OF

LSB 8 BITS OF

1 110000

SLAVE ADDRESS

BYTE 3 (MSB)

OF REGISTER

BYTE 2 OF

BYTE 1 OF

BYTE 0 (LSB)

OF REGISTER

11 1000 1

ACKNOWLEDGE

GENERATED BY

ADE7816

Figure 40. I2C Read Operation of a 32-Bit Register

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