ADF4351BCPZ datasheet(12/28 Pages) AD

12 / 28 page

ADF4351

Data Sheet

Rev. 0 | Page 12 of 28

MUXOUT AND LOCK DETECT

The multiplexer output on the ADF4351 allows the user to access

various internal points on the chip. The state of MUXOUT is

controlled by the M3, M2, and M1 bits in Register 2 (see Figure 26).

Figure 19 shows the MUXOUT section in block diagram form.

DGND

DVDD

CONTROL

MUX

MUXOUT

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N DIVIDER OUTPUT

DGND

RESERVED

THREE-STATE OUTPUT

DVDD

Figure 19. MUXOUT Schematic

INPUT SHIFT REGISTERS

The ADF4351 digital section includes a 10-bit RF R counter,

a 16-bit RF N counter, a 12-bit FRAC counter, and a 12-bit

modulus counter. Data is clocked into the 32-bit shift register

on each rising edge of CLK. The data is clocked in MSB first.

Data is transferred from the shift register to one of six latches

on the rising edge of LE. The destination latch is determined by

the state of the three control bits (C3, C2, and C1) in the shift

DB2, DB1, and DB0. Table 6 shows the truth table for these bits.

Figure 23 summarizes how the latches are programmed.

Table 6. Truth Table for the C3, C2, and C1 Control Bits

Control Bits

PROGRAM MODES

Table 6 and Figure 23 through Figure 29 show how the program

modes are set up in the ADF4351.

The following settings in the ADF4351 are double buffered: phase

value, modulus value, reference doubler, reference divide-by-2,

R counter value, and charge pump current setting. Before the part

uses a new value for any double-buffered setting, the following

two events must occur:

1. The new value is latched into the device by writing to the

appropriate register.

2. A new write is performed on Register 0 (R0).

For example, any time that the modulus value is updated,

value is loaded correctly. The divider select value in Register 4

(R4) is also double buffered, but only if the DB13 bit of

VCO

The VCO core in the ADF4351 consists of three separate VCOs,

each of which uses 16 overlapping bands, as shown in Figure 20,

to allow a wide frequency range to be covered without a large

VCO sensitivity (KV) and resultant poor phase noise and spur-

ious performance.

3.0

2.5

2.0

1.5

1.0

0.5

2.0

2.5

3.0

3.5

4.0

4.5

FREQUENCY (GHz)

Figure 20. VTUNE vs. Frequency

The correct VCO and band are selected automatically by the

VCO and band select logic at power-up or whenever Register 0

(R0) is updated.

VCO and band selection take 10 PFD cycles multiplied by the

value of the band select clock divider. The VCO VTUNE is discon-

nected from the output of the loop filter and is connected to an

internal reference voltage.

ADF4351BCPZ Datasheet(PDF) 12 Page - Analog Devices

ADF4351BCPZ Datasheet(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL