ADV7181DWBCPZ datasheet(16/24 Pages) AD

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ADV7181D

Data Sheet

Rev. 0 | Page 16 of 24

Table 8 provides the recommended ADC mapping for the ADV7181D.

Table 8. Recommended ADC Mapping

Mode

Required ADC Mapping

Analog Input Channel

Core

Configuration1

CVBS

ADC0

CVBS = AIN1

SDP

INSEL[3:0] = 0000

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 0010

YC/YC Auto

Y = ADC0

C = ADC1

Y = AIN7

C = AIN9

SDP

INSEL[3:0] = 0000

SDM_SEL[1:0] = 11

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 0010

Component YUV

Y = ADC0

U = ADC2

V = ADC1

Y = AIN10

U = AIN8

V = AIN6

SDP

INSEL[3:0] = 1001

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 0010

Component YUV

Y = ADC0

U = ADC2

V = ADC1

Y = AIN10

U = AIN8

V = AIN6

INSEL[3:0] = 0000

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 1010

SCART RGB

CBVS = ADC0

G = ADC1

B = ADC3

R = ADC2

CVBS = AIN4

G = AIN10

B = AIN6

R = AIN8

SDP

INSEL[3:0] = 0000

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 0010

Graphics

RGB Mode

G = ADC0

B = ADC2

R = ADC1

G = AIN2

B = AIN3

R = AIN5

INSEL[3:0] = 0000

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0010

VID_STD[3:0] = 1100

1 Configuration to format follow-on blocks in correct frame.

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