LTC2159 datasheet(22/32 Pages) LINER

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LTC2159

2159f

Digital Output Test Patterns

To allow in-circuit testing of the digital interface to the

A/D, there are several test modes that force the A/D data

outputs (OF, D15 to D0) to known values:

All 1s: all outputs are 1

All 0s: all outputs are 0

Alternating: outputs change from all 1s to all 0s on

alternating samples.

Checkerboard: outputs change from

10101010101010101 to 01010101010101010

on alternating samples.

The digital output test patterns are enabled by serially

programming mode control register A4. When enabled,

the test patterns override all other formatting modes: 2’s

complement, randomizer, alternate bit polarity.

Output Disable

The digital outputs may be disabled by serially program-

ming mode control register A3. All digital outputs includ-

ing OF and CLKOUT are disabled. The high-impedance

disabled state is intended for in-circuit testing or long

periods of inactivity—it is too slow to multiplex a data

bus between multiple converters at full speed. When the

outputs are disabled the ADC should be put into either

sleep or nap mode.

Sleep and Nap Modes

The A/D may be placed in sleep or nap modes to conserve

power. In sleep mode the entire device is powered down,

resulting in 1mW power consumption. The amount of

time required to recover from sleep mode depends on

the size of the bypass capacitors on VREF, REFH, and

REFL. For the suggested values in Figure 8, the A/D will

stabilize after 2ms.

applicaTions inForMaTion

InnapmodetheA/Dcoreispowereddownwhiletheinternal

referencecircuitsstayactive,allowingfasterwake-upthan

from sleep mode. Recovering from nap mode requires at

least 100 clock cycles. If the application demands very

accurate DC settling then an additional 50µs should be

allowed so the on-chip references can settle from the

slight temperature shift caused by the change in supply

current as the A/D leaves nap mode.

Sleep mode and nap mode are enabled by mode control

SDO (parallel programming mode).

DEVICE PROGRAMMING MODES

The operating modes of the LTC2159 can be programmed

by either a parallel interface or a simple serial interface.

The serial interface has more flexibility and can program

all available modes. The parallel interface is more limited

and can only program some of the more commonly used

modes.

Parallel Programming Mode

To use the parallel programming mode, PAR/SER should

be tied to VDD. The CS, SCK, SDI and SDO pins are binary

logic inputs that set certain operating modes. These pins

can be tied to VDD or ground, or driven by 1.8V, 2.5V, or

3.3V CMOS logic. When used as an input, SDO should be

driven through a 1kΩ series resistor. Table 2 shows the

modes set by CS, SCK, SDI and SDO.

Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)

DESCRIPTION

Clock Duty Cycle Stabilizer Control Bit

0 = Clock Duty Cycle Stabilizer Off

1 = Clock Duty Cycle Stabilizer On

SCK

Digital Output Mode Control Bit

0 = Full Rate CMOS Output Mode

1 = Double Data Rate LVDS Output Mode

(3.5mA LVDS Current, Internal Termination Off)

SDI/SDO

Power-Down Control Bits

00 = Normal Operation

01 = Not Used

10 = Nap Mode

11 = Sleep Mode (Entire Device Powered Down)

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