LTC2159

24

2159f

applicaTions inForMaTion

REGISTER A2: TIMING REGISTER (ADDRESS 02h)

D7

D6

D5

D4

D3

D2

D1

D0

X

X

X

X

CLKINV

CLKPHASE1

CLKPHASE0

DCS

Bits 7-4

Unused, Don’t Care Bits

Bit 3

CLKINV

Output Clock Invert Bit

0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)

1 = Inverted CLKOUT Polarity

Bits 2-1

CLKPHASE1: CLKPHASE0

Output Clock Phase Delay Bits

00 = No CLKOUT Delay (as shown in the Timing Diagrams)

Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.

Bit 0

DCS

Clock Duty Cycle Stabilizer Bit

0 = Clock Duty Cycle Stabilizer Off

1 = Clock Duty Cycle Stabilizer On

REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)

D7

D6

D5

D4

D3

D2

D1

D0

X

ILVDS2

ILVDS1

ILVDS0

TERMON

OUTOFF

OUTMODE1

OUTMODE0

Bit 7

Unused, Don’t Care Bit

Bits 6-4

ILVDS2: ILVDS0

LVDS Output Current Bits

000 = 3.5mA LVDS Output Driver Current

001 = 4.0mA LVDS Output Driver Current

010 = 4.5mA LVDS Output Driver Current

011 = Not Used

100 = 3.0mA LVDS Output Driver Current

101 = 2.5mA LVDS Output Driver Current

110 = 2.1mA LVDS Output Driver Current

111 = 1.75mA LVDS Output Driver Current

Bit 3

TERMON

LVDS Internal Termination Bit

0 = Internal Termination Off

1 = Internal Termination On. LVDS output driver current is 2x the current set by ILVDS2:ILVDS0.