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MK50DX256CLL7 Datasheet(PDF) 46 Page - Freescale Semiconductor, Inc |
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MK50DX256CLL7 Datasheet(HTML) 46 Page - Freescale Semiconductor, Inc |
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46 / 79 page ![]() 6.6.1.3 16-bit ADC with PGA operating conditions Table 27. 16-bit ADC with PGA operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit Notes VDDA Supply voltage Absolute 1.71 — 3.6 V VREFPGA PGA ref voltage VREF_OU T VREF_OU T VREF_OU T V 2, 3 VADIN Input voltage VSSA — VDDA V VCM Input Common Mode range VSSA — VDDA V RPGAD Differential input impedance Gain = 1, 2, 4, 8 Gain = 16, 32 Gain = 64 — — — 128 64 32 — — — kΩ IN+ to IN-4 RAS Analog source resistance — 100 — Ω 5 TS ADC sampling time 1.25 — — µs 6 Crate ADC conversion rate ≤ 13 bit modes No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 18.484 — 450 Ksps 7 16 bit modes No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 37.037 — 250 Ksps 8 1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. ADC must be configured to use the internal voltage reference (VREF_OUT) 3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other than the output of the VREF module, the VREF module must be disabled. 4. For single ended configurations the input impedance of the driven input is RPGAD/2 5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop in PGA gain without affecting other performances. This is not dependent on ADC clock frequency. 6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at 8 MHz ADC clock. 7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1 8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1 Peripheral operating requirements and behaviors K50 Sub-Family Data Sheet, Rev. 2, 4/2012. 46 Freescale Semiconductor, Inc. |
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