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MK50DX256CLL7 Datasheet(PDF) 77 Page - Freescale Semiconductor, Inc |
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MK50DX256CLL7 Datasheet(HTML) 77 Page - Freescale Semiconductor, Inc |
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77 / 79 page ![]() 1 A PTD7 B NC C NC D NC E NC F USB0_DP G VOUT33 H ADC0_DP1/ J OP1_DM1 K ADC1_DP3 1 L ADC0_DP3 2 PTD5 PTD6/ NC NC PTE2/ USB0_DM VREGIN OP0_DM0 OP1_DM0 ADC1_DM3 2 ADC0_DM3 3 PTD4/ PTD3 PTD2/ PTD1 PTE1/ NC VSS OP1_DP1 OP1_DP2 OP1_DM2 3 ADC1_SE18 4 PTC19 PTC18 PTC17 PTD0/ PTE0 PTE3 PTE5 TRI0_DM TRI0_DP OP1_DP5 4 XTAL32 5 PTC14 PTC15 PTC11/ PTC16 VDD VDDA VREFH NC NC OP1_DP4 5 EXTAL32 6 PTC13 PTC12 PTC10 PTC9 VDD VSSA VREFL ADC1_SE22 PTA0 VBAT 6 VSS 7 PTC8 PTC7 PTC6/ PTC5/ VDD VSS VSS PTE4/ PTA2 NC 7 RTC_ 8 PTC4/ PTC3/ PTC2 PTC1/ PTB23 PTB22 PTB3 PTA1 PTA4/ PTA12 8 PTA13/ 9 NC PTC0 PTB19 PTB18 PTB17 PTB21 PTB2 PTA3 NC PTA14 9 PTA15 10 NC PTB16 PTB11 PTB10 PTB9 PTB20 PTB1 NC NC VSS 10 VDD 11 A NC B NC C NC D PTB8 E PTB7 F PTB6 G PTB0/ H NC J RESET_b K PTA19 11 L PTA18 LLWU_P4 WAKEUP_B CMP0_IN5/ CMP1_IN5/ VREF_OUT/ ADC1_DM0/ PGA1_DM/ ADC1_DP0/ PGA1_DP/ OP0_DP4/ ADC0_SE23/ CMP1_IN3/ DAC0_OUT/ OP0_DP5/ ADC1_SE23/ CMP2_IN3/ CMP0_IN4/ TRI0_OUT/ ADC0_DM0/ PGA0_DM/ ADC0_DP0/ PGA0_DP/ LLWU_P3 OP0_DP2/ ADC0_SE22/ CMP2_IN2/ OP1_OUT/ ADC1_SE16/ ADC1_DM1/ OP1_DP0/ ADC1_DP1/ CMP2_IN5/ LLWU_P2 OP0_DP1/ ADC0_SE21/ CMP1_IN2/ OP0_OUT/ ADC0_SE16/ ADC0_DM1/ OP0_DP0 LLWU_P5 LLWU_P1 LLWU_P0 LLWU_P6 LLWU_P9 LLWU_P12 LLWU_P13 LLWU_P11 LLWU_P10 LLWU_P7 LLWU_P15 LLWU_P14 LLWU_P8 Figure 30. K50 104 MAPBGA Pinout Diagram 9 Revision History The following table provides a revision history for this document. Table 53. Revision History Rev. No. Date Substantial Changes 1 3/2012 Initial public release Table continues on the next page... Revision History K50 Sub-Family Data Sheet, Rev. 2, 4/2012. Freescale Semiconductor, Inc. 77 |
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