MPC8377E datasheet(113/127 Pages) FREESCALE

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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

113

23.3

Suggested PLL Configurations

This table shows suggested PLL configurations for different input clocks (LBCM = 0).

0001

11.5:1

0001

11.5:1

0010

02:1

0010

02:1

0010

02:1

0010

12.5:1

0010

12.5:1

0010

12.5:1

0011

03:1

0011

03:1

0011

03:1

0011

13.5:1

0011

13.5:1

0011

13.5:1

0100

04:1

0100

04:1

0100

04:1

Notes:

1. Core VCO frequency = Core frequency

× VCO divider. Note that VCO divider has to be set properly so that the core VCO

frequency is in the range of 800–1600 MHz.

Table 80. Example Clock Frequency Combinations

eLBC

e300 Core

Ref

LBCM DDRCM SVCOD SPMF

Sys

VCO

1,2 CSB

1,3 DDR data

rate

1,4

× 1 × 1.5 × 2 × 2.5 × 3

25.0

500

125

250

62.5

31.3

15.6

————

375

25.0

600

150

300

75 6

37.5

18.8

—

375

450

33.3

667

167

333

83.3 6

41.6

20.8

—

333

416

500

33.3

533

133

267

66.7

33.3

16.7

—

333

400

Table 79. e300 Core PLL Configuration (continued)

RCWLR[COREPLL]

core_clk : csb_clk Ratio

VCO Divider 1

0–1

2–5

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