SP9604DS/03

SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter

© Copyright 2000 Sipex Corporation

8

Figure 3. Latch Control Options — (a) Semi–Transparent Latch Mode; (b) Fully–Transparent Latch Mode

(a)

(b)

Figure 4. Timing

H

L

H

L

H

L

CLR

XFER

WR2

140ns, t

H

L

H

L

H

L

WR2

CS

WR1

140ns, t

Data Transfer from

Input Register to DAC's

Loads Input Data to

First Set of Latches

WR

XFER

on-reset. Using this feature, the SP9604 can be

configured such that during power-up, the sec-

ond register will be digitally “zeroed”, produc-

ing a zero volt output at each of the four DAC

outputs. This is achieved by powering the unit

up with XFER in a high state. Thus, with no

external circuitry, the SP9604 can be powered up

with the analog outputs at a known, zero volt

output level.

Temporarily forcing all DAC outputs to 0V

Set WR1=1, CS=1, WR2=0, XFER=0. The DAC

registers can be temporarily forced to 1000 0000

0000 by bringing the CLR pin low. This will force

the DAC outputs to 0V, while the CLR pin remains

low. When the CLR pin is brought back high, the

digital code at the DAC registers will again appear

at the DAC's digital inputs, and the analog outputs

will return to their previous values.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

CLR

REF IN

GND

B1/B2

XFER

WR2

WR1

CS

SP9604

+5V –5V

12–Bit

Data

Bus

+3V

Reference

GND

Address

Decode &

Control

DAC Strobe

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

CLR

REF IN

GND

B1/B2

XFER

WR2

WR1

CS

SP9604

+5V –5V

12–Bit

Data

Bus

+3V

Reference

GND

Address

Decode &

Control