SP9604 datasheet(3/11 Pages) SIPEX

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SP9604DS/03

SP9604 Quad, 12-Bit, Low Power Voltage Output D/A Converter

CODE

4095

DNLE, INLE Plots

+0.25 lsb

DNLE

-0.25 lsb

+0.25 lsb

INLE

-0.25 lsb

SPECIFICATIONS (continued)

(Typical @ 25˚C, T

MIN ≤ TA≤TMAX; VDD = +5V, VSS = -5V, VREF = +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)

PARAMETER

MIN.

TYP.

MAX.

UNITS

CONDITIONS

STABILITY

Gain

ppm/˚C

MIN to tMAX

Bipolar Zero

ppm/˚C

MIN to tMAX

SWITCHING CHARACTERISTICS

DS Data Set Up Time

140

100

to rising edge of WR1

DN Data Hold Time

Figure 4

WR Write Pulse Width

140

100

XFER Transfer Pulse Width

140

100

WC Total Write Command

280

200

POWER REQUIREMENTS

Note 5

+5V, +3%; Note 4, 5

–J, –K

-5V, +3%; Note 4, 5

–J, –K

Power Dissipation

ENVIRONMENTAL AND MECHANICAL

Operating Temperature

-J, -K

+70

°C

Storage

-60

+150

°C

Package

-_P

28-pin Plastic DIP

-_S

28-pin SOIC

Notes:

Integral Linearity, for the SP9604, is measured as the arithmetic mean value of the magnitudes of

the greatest positive deviation and the greatest negative deviation from the theoretical value for any

given input condition.

Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two

adjacent digital input codes.

1 LSB = 2*V

REF/4,096.

REF = 0V.

The following power up sequence is recommended to avoid latch up: VSS (-5V), VDD (+5V), REF IN.

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