MPC5554 datasheet(39/58 Pages) FREESCALE

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Electrical Characteristics

MPC5554 Microcontroller Data Sheet, Rev. 4

Freescale Semiconductor

Data setup time for inputs

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)7

Master (MTFE = 1, CPHA = 1)

tSUI

–4

—

Data hold time for inputs

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)7

Master (MTFE = 1, CPHA = 1)

tHI

–4

—

–4

—

–4

—

Data valid (after SCK edge)

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

tSUO

—

Data hold time for outputs

Master (MTFE = 0)

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

tHO

–5

5.5

–5

—

–5

5.5

–5

—

–5

5.5

–5

—

1 All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types

of S or SH have an additional delay based on the slew rate. DSPI timing is specified at: VDDEH = 3.0–5.25 V;TA = TL to TH;

and CL = 50 pF with SRC = 0b11.

2 Speed is the nominal maximum frequency. Max. speed is the maximum speed allowed including frequency modulation (FM).

82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM; and

132 MHz parts allow for 128 MHz system clock + 2% FM.

3 The minimum SCK cycle time restricts the baud rate selection for the given system clock rate.

These numbers are calculated based on two MPC55xx devices communicating over a DSPI link.

4 The actual minimum SCK cycle time is limited by pad performance.

5 The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].

6 The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].

7 This number is calculated using the SMPL_PT field in DSPI_MCR set to 0b10.

Table 26. DSPI Timing1’ 2 (continued)

Spec

Characteristic

Symbol

80 MHz

112 MHz

132 MHz

Unit

Min.

Max.

Min.

Max.

Min.

Max.

MPC5554 Datasheet(PDF) 39 Page - Freescale Semiconductor, Inc

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