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SL1062A Datasheet(PDF) 7 Page - System Logic Semiconductor

Part # SL1062A
Description  Low Voltage Transmission Circuit with Dialler Interface
PDF  9 Pages
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Manufacturer  SLS [System Logic Semiconductor]
Direct Link  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL1062A Datasheet(HTML) 7 Page - System Logic Semiconductor

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SL1062A
System Logic
Semiconductor
SLS
ELECTRICAL CHARACTERISTICS(I
line = 11 to 140 mA; VEE = 0 V; f = 800 Hz;Tamb = 25
°C; unless
other specified)
Symbol
Parameter
Test Conditions
Guaranteed Limits
Unit
Min
Typ
Max
∆G
vf
Gain Variation with
Frequency Reference to
800 Hz
f = 300 and 3400 Hz
-
±0.2
-
dB
∆G
vT
Gain Variation with
Temperature Referenced to
25
°C
without R6; Iline =50 mA;
Tamb = -25 and +75
°C
-
±0.2
-
dB
Vo(rms)
Output Voltage (RMS value)
THD = 2%; sine wave drive:
R4 = 100 K
Ω;
Iline = 15 mA; Ip = 0 mA
RL = 150
Ω
RL = 450
Ω
0.22
0.3
-
-
-
-
V
Vo(rms)
Output Voltage (RMS value)
THD=10%; R4=100 K
Ω; I
line
= 4 mA; RL = 150
Ω
-
15
-
mV
Vno(rms)
Noise Output Voltage (RMS
value)
Iline = 15 mA; R4=100K
Ω
IR open-circuit
psophometrically weighted;
RL =300
Ω
-
50
-
µV
Gain Adjustment Input GAR (pin 5)
∆G
v
Receiving Amplifier Gain
Variation by Adjustment of
R4 between GAR and OR
-11
-
0
dB
Mute Input (pin 12)
VIH
HIGH Level Input Voltage
1.5
-
VCC
V
VIL
LOW Level Input Voltage
-
-
0.3
V
IMUTE
Input Current
-
-
15
µA
Raduction of Gain
∆G
v
MIC+ or MIC- to LN
MUTE = LOW
-
70
-
dB
Gv
Voltage Gain from DTMF to
QR
R4 = 100 K
Ω
RL = 300
Ω
-
-17
-
dB
Automatic Gain Control Input AGC (pin 15)
∆G
v
Controlling the Gain from IR
to QR and the Gain from
MIC+, MIC- to LN
Gain Control Range
R6 = 110 K
Ω
(between AGC and VEE)
Iline = 70 mA
-
-5.8
-
dB
IlineH
Highest Line Current for
Maximum Gain
-
23
-
mA
IlineL
Lowest Line Current for
Minimum Gain
-
61
-
mA



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