Valid Data

DA[9:0]

SELECTIQ

WRTIQ

CLKIQ

RESETIQ

IOUT

or

IOUT

DAC5652A

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SLAS535D – SEPTEMBER 2007 – REVISED AUGUST 2012

Correct pairing of the A- and B-channel data is done by RESETIQ. In interleaved mode, the clock input CLKIQ is

divided by two, which would translate to a non-deterministic relation between the rising edges of the CLKIQ and

CLKDACIQ. RESETIQ ensures, however, that the correct position of the rising edge of CLKDACIQ with respect

to the data at the input of the DAC latch is determined. CLKDACIQ is disabled (low) when RESETIQ is high.

Figure 16. Single-Bus Interleaved Mode Operation

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