74ACT11191

SYNCHRONOUS 4BIT UP/DOWN BINARY COUNTER

SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993

POST OFFICE BOX 655303

POST OFFICE BOX 1443

2−4

typical load, count, and inhibit sequences

Illustrated below is the following sequence:

1.

Load (preset) to binary thirteen

2.

Count up to fourteen, fifteen (maximum), zero, one, and two

3.

Inhibit

4.

Count down to one, zero (minimum), fifteen, fourteen, and thirteen.

A

B

C

D

CLOCK

D/U

MAX/MIN

QA

QD

QC

QB

Load

Count Up

Inhibit

Count Down

13

14

15

0

1

2

2

2

1

0

151413

Data

Inputs

RCO

CTEN

LOAD