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74ACT11191DBLE Datasheet(PDF) 1 Page - Texas Instruments |
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74ACT11191DBLE Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 9 page ![]() 74ACT11191 SYNCHRONOUS 4BIT UP/DOWN BINARY COUNTER SCAS106A − D3455, FEBRUARY 1990 − REVISED APRIL 1993 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001 Copyright 1993, Texas Instruments Incorporated 2−1 • Inputs Are TTL-Voltage Compatible • Single Down/Up Count Control Line • Look-Ahead Circuitry Enhances Speed of Cascaded Counters • Fully Synchronous in Count Modes • Asynchronously Presettable With Load Control • Flow-Through Architecture Optimizes PCB Layout • Center-Pin V CC and GND Configurations to Minimize High-Speed Switching Noise • EPICt (Enhanced-Performance Implanted CMOS) 1- mm Process • Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs description The 74ACT11191 is a synchronous, 4-bit binary reversible up/down counter. A synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock input if the enable input (CTEN) is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up and when D/U is high, it counts down. These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter will be dictated solely by the condition meeting the stable setup and hold times. logic symbol† B 12 20 18 13 14 17 11 19 CLK C D A G1 9 8 3 2 M2 [DOWN] M3 [UP] 1,2−/1,3+ G4 C5 6,1,4 3(CT=15)Z6 2(CT=0)Z6 CTRDIV16 RCO MAX/MIN 10 1 5D [1] [2] [4] [8] CTEN LOAD D/U QA QB QC QD † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RCO QA QB GND GND GND GND QC QD MAX/MIN D/U CLK A B VCC VCC C D CTEN LOAD DW OR N PACKAGE (TOP VIEW) EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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