74ACT11646

OCTAL BUS TRANSCEIVER AND REGISTER

WITH 3STATE OUTPUTS

SCAS061A − D2957, JULY 1987 − REVISED APRIL 1993

POST OFFICE BOX 655303

POST OFFICE BOX 1443

2−3

FUNCTION TABLE

INPUTS

DATA I/O

OPERATION OR FUNCTION

G

DIR

CAB

CBA

SAB

SBA

A1 THRU A8

B1 THRU B8

OPERATION OR FUNCTION

X

X

↑

X

X

X

Input

†

Unspecified†

Store A, B unspecified†

X

XX

↑

XX

Input

Unspecified†

Unspecified†

Input

Store A, B unspecified†

Store B, A unspecified†

H

X

↑

↑

X

X

Input

Input

Store A and B Data

H

X

H or L

H or L

X

X

Input

Input

Store A and B Data

Isolation, hold storage

L

L

X

X

X

L

Output

Input

Real-Time B Data to A Bus

L

L

X

H or L

X

H

Output

Input

Real-Time B Data to A Bus

Stored B Data to A Bus

L

H

X

X

L

X

Input

Output

Real-Time A Data to B Bus

L

H

H or L

X

H

X

Input

Output

Real-Time A Data to B Bus

Stored A Data to B Bus

† The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e.,

data at the bus pins will be stored on every low-to-high transition on the clock inputs.

functional block diagram (positive logic)

To Seven Other Channels

B1

26

A1

2

SAB

CAB

SBA

CBA

DIR

G1

27

28

15

16

14

1

Channels

1 of 8

1D

C1

C1

1D

5

5

B8

B7

B6

B5

B4

B3

B2

B1

17

18

19

20

23

24

25

26

A8

A7

A6

A5

A4

A3

A2

A1

SAB

CAB

SBA

CBA

DIR

G

13

12

11

10

5

4

3

2

27

28

15

16

14

1

1

6D

7

7

4D

G7

C6

G5

C4

3 EN2 [AB]

3 EN1 [BA]

G3

2

1

≥1

≥1

1

‡ This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.