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AFE5808ZCF Datasheet(PDF) 64 Page - Texas Instruments |
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AFE5808ZCF Datasheet(HTML) 64 Page - Texas Instruments |
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64 / 68 page ![]() AFE5808 SLOS688C – SEPTEMBER 2010 – REVISED APRIL 2012 www.ti.com REVISION HISTORY Changes from Original (September 2010) to Revision A Page • Changed From: Product Preview To: Production Data ........................................................................................................ 1 Changes from Revision A (December 2010) to Revision B Page • Added text to the pin Description for B9~ B2 (ACT1...ACT8) .............................................................................................. 4 • Added text to the L4 and M4 Pin Descriptions ..................................................................................................................... 5 • Changed the ELECTRICAL CHARACTERISTICS condition statement ............................................................................... 6 • Changed the Common-mode voltage values From: MIN 0.75 V / MAX 1 V To: 0.75 V TYP .............................................. 6 • Added Note 1 ........................................................................................................................................................................ 6 • Changed the ELECTRICAL CHARACTERISTICS condition statement ............................................................................... 7 • Changed the Gain Matching Test Conditions From: 0.1V< VCNTL<1.3V (Dev-to-Dev) To: 0.1V< VCNTL<1.1V(Dev- to-Dev). ................................................................................................................................................................................. 7 • Added to the Gain Matching Test Conditions: 0.1V< VCNTL<1.1V (Dev-to-Dev), Temp = 0°C and 85°C .......................... 7 • Changed the Gain Matching Test Conditions From: 1.3V< VCNTL<1.5V (Dev-to-Dev) To: 1.1V< VCNTL<1.5V(Dev-to- Dev). ..................................................................................................................................................................................... 7 • Changed the Output Offset values From: MIN = -60 LSB / MAX = 60 LSB To: MIN = -75 LSB / MAX = 75 LSB .............. 7 • Changed the ELECTRICAL CHARACTERISTICS condition statement ............................................................................... 8 • Changed en (RTO) and en (RTI) Test Conditions From: LNA = 24dB To: 18dB ................................................................. 8 • Changed the ELECTRICAL CHARACTERISTICS condition statement ............................................................................... 9 • Changed the AVDD (3.3V) Current - TGC low noise mode, no signal Max value From: 225 mA To: 235 mA ................... 9 • Changed the TYPICAL CHARACTERISTICS condition statement .................................................................................... 11 • Changed all -40°C to 85°C To 0°C to 85°C ........................................................................................................................ 21 • Changed the ADC latency test Conditions and Typ value. ................................................................................................ 21 • Changed Figure 58 ............................................................................................................................................................. 22 • Added t8 to the SPI Timing Characteristics table ................................................................................................................ 24 • Updated the SDOUT description in the Register Readout section ..................................................................................... 24 • Changed Figure 60 ............................................................................................................................................................. 24 • Changed the Text Note following Figure 61 ....................................................................................................................... 25 • Changed the LOW_LATENCY Desctiption ......................................................................................................................... 26 • Changed the VOLTAGE-CONTROLLED-ATTENUATOR. Deleted the last sentence of paragraph two ........................... 51 • Changed Figure 85, Removed the Single-Ended Input at VCNTLM image ....................................................................... 51 • Changed the ADC Reference Circuit section. Added text to the end of paragraph two .................................................... 59 • Changed the Power Management Priority section. Added text to the end of paragraph ................................................... 60 • Changed the Priority column in Table 13 ........................................................................................................................... 60 64 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Link(s): AFE5808 |
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