AFE8220TPZPQ1 datasheet(13/49 Pages) TI1

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Control Interface

SPI Interface

SCK

MOSI

MISO

INSTRUCTI

DATA

REG_ADDR

MEM

MEM_ADDR

AFE8220-Q1

www.ti.com....................................................................................................................................................... SBAS455A – JANUARY 2009 – REVISED JULY 2009

Configuration and control data are written to the AFE8220 via the control interface. The control interface supports

two protocols, SPI and I2C. If the CTRL_MODE pin is tied low, then an SPI interface is implemented. If

CTRL_MODE is tied high, then an I2C protocol-compatible interface is implemented.

The SPI interface consists of four signals: a serial clock (SCK), an active-low chip select (CS), a serial data input

(MOSI: master out, slave in), and a serial data output (MISO: master in, slave out). Data are transferred in

groups of 32 bits. The first 16 bits are the instruction, which indicates:

1. If data are to be written or to be read;

2. If the data target is a register or RAM; and

3. The address of the data target.

The second 16 bits are the data transfer, which is input on MOSI for a write cycle or output on MISO for a read

cycle.

Figure 4 shows an SPI write cycle. The cycle is initiated by the high-to-low transition of the CS line. 32 SCK

pulses clock the instruction and the data into the MOSI line. Data are clocked in MSB first. The first 16 bits are

the instruction. There are two possible write cycle instructions: register write and memory write. The formats for

these instructions are shown in Figure 5 and Figure 6, respectively.

The only information required for a register write is the five-bit register address (REG_ADDR). For a memory

write, both the two-bit memory select (MEM) plus the eight-bit memory address (MEM_ADDR) are required.

Following the 16-bit instruction, the 16-bit data word is clocked in, again MSB first. At the end of the write cycle,

this data word is written to the appropriate register or memory location in the AFE8220.

Figure 4. SPI Control Interface Write Cycle

Figure 5. Register Write Instruction Format

Figure 6. Memory Write Instruction Format

Figure 7 shows the SPI interface read cycle. It is similar to the write cycle, except that instead of the data word

being clocked into MOSI during the second half of the cycle, the data word is clocked out of MISO. Note that only

For reading and writing, data block transfers are supported. For a block transfer, multiple data words are

transmitted following the memory read or write instruction. The data words are read from or written sequentially

starting at the address contained in the instruction. The sequential access terminates when the CS line goes

high. Figure 8 shows a register block read cycle. In the illustration, three succeeding register locations are read

starting at address N. The block write cycle is similar except, of course, data are clocked into MOSI.

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