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DLPC100 Datasheet(PDF) 8 Page - Texas Instruments |
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DLPC100 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 25 page  DLPC100 DLPS019B – DECEMBER 2009 – REVISED DECEMBER 2010 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL I/O CLOCK DESCRIPTION TYPE SYSTEM NAME NO. MEM_DQ9 B7 B3 MEM_CLK Bidirectional data 9 for the SDRAM MEM_DQ10 E7 B3 MEM_CLK Bidirectional data 10 for the SDRAM MEM_DQ11 A2 B3 MEM_CLK Bidirectional data 11 for the SDRAM MEM_DQ12 D6 B3 MEM_CLK Bidirectional data 12 for the SDRAM MEM_DQ13 B5 B3 MEM_CLK Bidirectional data 13 for the SDRAM MEM_DQ14 D5 B3 MEM_CLK Bidirectional data 14 for the SDRAM MEM_DQ15 A4 B3 MEM_CLK Bidirectional data 15 for the SDRAM LED Driver Interface BLU_PWM C6 O3 CLK_IN Blue LED PWM signal used to control the LED current RED_PWM C3 O3 CLK_IN Red LED PWM signal used to control the LED current GRN_PWM D3 O3 CLK_IN Green LED PWM signal used to control the LED current BLU_STROBE F1 O1 CLK_IN Blue LED enable RED_STROBE G2 O1 CLK_IN Red LED enable GRN_STROBE F2 O1 CLK_IN Green LED enable LED_FAULT A8 I4 Async LED fault indication. Signal forces LEDDRV_ON low and RGB strobes low LED_ENABLE T8 I5 Async LED enable. Signal forces LEDDRV_ON low and RGB strobes low. LEDDRV_ON F3 O1 CLK_IN LED driver enable RESERVED B1 I1 Async Not used. Reserved for future use. RESERVED C2 O1 Async Not used. Reserved for future use. Impedance Control(2) RUP2 PWR N/A Bank 4 control RDN2 PWR N/A Bank 4 control RUP3 PWR N/A Bank 5 control RDN3 PWR N/A Bank 5 control RUP4 PWR N/A Bank 7 control RDN4 PWR N/A Bank 7 control Power and Ground(2) P1P2V PWR N/A 1.2 V core power P2P5V_DPLL PWR N/A 2.5 V filtered power for internal PLL P1P8V PWR N/A 1.8 V I/O power P2P5V PWR N/A 2.5 V I/O power P3P3V PWR N/A 3.3 V I/O power GND PWR N/A Common digital ground GNDA PWR N/A Common PLL ground (2) To see how these are connected, see the reference schematic 8 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): DLPC100 |
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