BBin

DACout

Gain

Pilot

Insertion

AntCal

Insertion

Power

Meter

16

BBFR

1

Wide

Band

DUC

Wide

Band

DUC

Medium

Band

DUC

Medium

Band

DUC

Medium

Band

DUC

Medium

Band

DUC

NarrowBand DUC

NarrowBand DUC

NarrowBand DUC

NarrowBand DUC

NarrowBand DUC

NarrowBand DUC

NarrowBand DUC

NarrowBand DUC

NarrowBand DUC

NarrowBand DUC

NarrowBand DUC

NarrowBand DUC

+

CFR

Fractional

Resampler

Circular

Limiter

GC5328

JTAG

MPU Interface

RESETB SYNC

3

SYNC

OUT

TCK

TRST

TI

TMS

TD

16

10

4

BBclk

DPDclk

SYNC

BB

PLL

DPD

PLL

Real to Complex

Feedback

Equalizer

Feedback Mixer

and NL Correction

Bulk Interpolation

+ Mixer

Transmit

Equalizer

DPD

ADC

Interface

DAC

Interface

Capture Buffers

DUCs in

1-Chn Mode

DUCs in

2-Chn Mode

DUCs in

6-Chn Mode

BB Clock Domain

DPD Clock Domain

B0279-03

Envelope

Interface

To Capture

Buffer

To Capture

Buffer

To Capture

Buffer

Pilot

Insertion

ADCin

(LVDS)

16

ADCin

(LVDS)

2

16

MAGclk

MAGout

38

Active Only in Dual

Antenna Mode

GC5328

SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009

www.ti.com

The CFR block has four serial stages of peak detection and cancellation. The CFR block cancellation filter can

be programmed as real or complex. The CFR peak-reduced output is routed to the Farrow resampler. The

Farrow resampler resamples the CFR output to the DPD clock rate. The Farrow resampler block also has a

complex mixer for composite carrier frequency offset.

The DPD subsystem has a circular limiter, nonlinear DPD correction, and a transmit equalizer. The DPD

correction can reduce the follow-on circuitry distortion products. The DPD output is sent to the BUC. The BUC

provides a post-DPD interpolation, and also provides a complex mixer for frequency offset. The DAC interface

converts the BUC signal output to the interleaved IQ or parallel IQ output signals for the DAC5682Z or DAC5688.

The CB block captures the selected internal reference signal, and the feedback block in two up to 4K capture

buffers. The signal capture can be based on an externally timed event (standard capture buffer), delay after a

timed event, or signal statistics (smart capture buffer). Normally the DPD input and feedback output are selected.

The capture buffers are stored and read by the microprocessor.

The FB block receives the LVDS ADC information and performs signal processing to downconvert the received

signal to 0IF. The FB block also has a feedback-path receive equalizer.

Figure 2. GC5328 Functional Block Diagram

2

Submit Documentation Feedback

Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s): GC5328