GC5328 datasheet(21/27 Pages) TI1

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TCK

TDI

TDO

1/f

TCK

su(TDI)

h(TDI)

d(TDO)

T0289-01

p(TCKL)

p(TCKH)

DAC[15:0]P

DAC[15:0]N

DACCLK

DACCLKC

SKW(DAC)

T0290-01

1/f

CLK(DAC)

GC5328

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SLWS218A – OCTOBER 2009 – REVISED OCTOBER 2009

JTAG SWITCHING CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

TEST CONDITIONS PARAMETER

MIN

MAX

UNIT

fTCK

JTAG clock frequency

MHz

tp(TCKL)

JTAG clock low period

tp(TCKH)

JTAG clock high period

tsu(TDI)

Input data setup time before TCK

↑

Valid for TDI and TMS

th(TDI)

Input data hold time after TCK

↑

Valid for TDI and TMS

td(TDO)

Output data delay from TCK

↓

Figure 14. JTAG Timing Specifictions

TX SWITCHING CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

HSTL MODE – DDR ex. DAC5682

fCLK(DAC)

DAC output clock frequency

RL = 100 Ω

(1)

300

MHz

tSKW(DAC)

DACCLK to DAC data

RL = 100 Ω

(2)

TBD

(1)

Because the output clock is DDR, the data rate is 2× the fCLK rate; fCLK(DAC) = (BUC Interp × DPDClk / 2).

(2)

tSKW(DAC) data clock-to-data is measured during characterization.

Figure 15. TX Timing Specifications (HSTL – DDR)

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