INA223

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SBOS528 – JUNE 2012

BUS OVERVIEW

The INA223 is compatible with both two-wire and SMBus interfaces. These protocols are essentially compatible

with one another. The two-wire interface is used throughout this data sheet as the primary example, with the

SMBus protocol specified only when a difference between the two systems is considered.

Two bidirectional lines, SCL and SDA, connect the INA223 to the bus. Both SCL and SDA are open-drain

connections.

The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The

bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and

generates start and stop conditions.

To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a

high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge

of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the

slave being addressed responds to the master by generating an acknowledge bit and pulling SDA low.

Data transfer is then initiated and eight bits of data are sent, followed by an acknowledge bit. During data

transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a

start or stop condition.

After all data have been transferred, the master generates a stop condition, indicated by pulling SDA from low to

high while SCL is high. The INA223 includes a 28-ms timeout on its interface to prevent locking up the bus.

Serial Bus Address

To communicate with the INA223, the master must first address slave devices through a slave address byte. The

slave address byte consists of seven address bits, and a direction bit that indicates the intent of executing a read

or write operation.

The INA223 has one address pin, A0. Table 6 describes the pin logic levels for each of the four possible

addresses. The state of the A0 pin is sampled on every bus communication and should be set before any activity

on the interface occurs. The address pins are read at the start of each communication event.

Table 6. INA223 Address Pins and Slave Addresses

A0

ADDRESS

GND

1000000

1000001

SDA

1000010

SCL

1000011

Serial Interface

The INA223 operates only as a slave device on both the two-wire bus and SMBus. Connections to the bus are

made through the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike

suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The INA223

supports the transmission protocol for fast (1 kHz to 400 kHz) and high-speed (1 kHz to 3.4 MHz) modes. All

data bytes are transmitted most significant byte first.

Copyright © 2012, Texas Instruments Incorporated

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