MSP430F5333IPZ datasheet(39/101 Pages) TI1

39 / 101 page

MSP430F533x

www.ti.com

SLAS721B – AUGUST 2010 – REVISED AUGUST 2012

Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

Voltage applied at VCC to VSS

–0.3 V to 4.1 V

Voltage applied to any pin (excluding VCORE, VBUS, V18)(2)

–0.3 V to VCC + 0.3 V

Diode current at any device pin

±2 mA

Storage temperature range, Tstg

(3)

–55°C to 150°C

Maximum junction temperature, TJ

95°C

(1)

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltages referenced to VSS. VCORE is for internal device use only. No external dc loading or voltage should be applied.

(3)

Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

Recommended Operating Conditions

MIN

NOM

MAX

UNIT

PMMCOREVx = 0

1.8

3.6

Supply voltage during program execution and flash

PMMCOREVx = 0, 1

2.0

3.6

VCC

programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 =

PMMCOREVx = 0, 1, 2

2.2

3.6

DVCC = VCC)

(1) (2)

PMMCOREVx = 0, 1, 2, 3

2.4

3.6

Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 =

VSS

DVSS2 = DVSS3 = VSS)

TA = 0°C to 85°C

1.55

3.6

VBAT,RTC

Backup-supply voltage with RTC operational

TA = –40°C to 85°C

1.70

3.6

VBAT,MEM

Backup-supply voltage with backup memory retained.

TA = –40°C to 85°C

1.20

3.6

Operating free-air temperature

I version

–40

°C

Operating junction temperature

I version

–40

°C

CBAK

Capacitance at pin VBAK

4.7

CVCORE

Capacitor at VCORE

470

CDVCC/

Capacitor ratio of DVCC to VCORE

CVCORE

PMMCOREVx = 0,

1.8 V

≤ VCC ≤ 3.6 V

8.0

(default condition)

PMMCOREVx = 1,

12.0

Processor frequency (maximum MCLK frequency)(3)(4)

2 V

≤ VCC ≤ 3.6 V

fSYSTEM

MHz

(see Figure 1)

PMMCOREVx = 2,

16.0

2.2 V

≤ VCC ≤ 3.6 V

PMMCOREVx = 3,

20.0

2.4 V

≤ VCC ≤ 3.6 V

(1)

It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be

tolerated during power up and operation.

(2)

The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold

parameters for the exact values and further details.

(3)

The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the

specified maximum frequency.

(4)

Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

MSP430F5333IPZ Datasheet(PDF) 39 Page - Texas Instruments

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