TFB2002BI

FUTUREBUS+ I/O CONTROLLER

SLLS182 – AUGUST 1994

4

POST OFFICE BOX 655303

Terminal Functions

host interface (continued)

TERMINAL

I/O

FROM/TO

DESCRIPTION

NAME

NO.

I/O

FROM/TO

DESCRIPTION

MORE*

194

I

Host interface

Host cycle is part of a longer transaction input. MORE* is used in DMA writes to indicate

that this transaction should be included in the same tenure with the next host-interface

transaction. MORE* is used in reads to indicate that MR* should be asserted during the

Futurebus+ transaction.

TBST*

193

I/O

Host interface

Host-transaction burst request

TR/W*

22

I/O

Host interface

Host-interface read or write

TSIZE < 1:0 >

1, 2

I

Host interface

Host-interface transaction size input:

LL

LH

Word (32 bits or greater)

B t (8 bit )

LH

HL

Byte (8 bits)

Half word (16 bits)

HL

HH

Half word (16 bits)

Three bytes (24 bits)

other module interface signals

TERMINAL

I/O

FROM/TO

DESCRIPTION

NAME

NO.

I/O

FROM/TO

DESCRIPTION

ARBERR< 1:0 >

127,

I

Arbiter

Arbitration error input:

126

LL

LH

No error

ACO

d AC1

t d d i

h

3

LH

HL

ACO and AC1 asserted during phase 3

Arbitration comparison error

HL

HH

Arbitration com arison error

Arbitration time-out error (phase 2 or 4)

REFCLK

122

I

Module

Clock input. A 25-MHz, 50%

± 5% duty-cycle signal is recommended; any frequency

between 20 MHz and 40 MHz and duty cycle of 50%

± 5% can be tolerated.

CSR bus

TERMINAL

I/O

FROM/TO

DESCRIPTION

NAME

NO.

I/O

FROM/TO

DESCRIPTION

CA < 11:0 >

164, 163, 162,

160, 159, 158,

156, 155, 154,

152, 151, 150

I

CSR bus

CSR bus address

CD < 7:0 >

147, 146, 144,

143, 142, 140,

139, 138

I/O

CSR bus

CSR bus data

CDP

148

I/O

CSR bus

CSR bus data odd parity

CCE*

135

I

CSR bus

CSR bus chip enable

COE*

136

I

CSR bus

CSR bus output enable

CWE*

134

I

CSR bus

CSR bus write enable