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TFB2002B Datasheet(PDF) 6 Page - Texas Instruments

Part # TFB2002B
Description  FUTUREBUS I/O CONTROLLER
PDF  13 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TFB2002B Datasheet(HTML) 6 Page - Texas Instruments

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TFB2002BI
FUTUREBUS+ I/O CONTROLLER
SLLS182 – AUGUST 1994
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Terminal Functions
interface to TFB2022A (continued)
TERMINAL
I/O
FROM/TO
DESCRIPTION
NAME
NO.
I/O
FROM/TO
DESCRIPTION
HADEC < 3:0 >
9, 10,
I
TFB2022A DPU
Host address decode. Address decoding for the host-interface address:
11, 13
Slave encoding:
Master encoding:
LLLL
LLLH
LLHL
LLHH
LHLL
LHLH
LHHL
LHHH
HLLL
HLLH
HLHL
HLHH
HHLL
HHLH
HHHL
HHHH
Unselected
Host memory
Host extended-unit space
Host CSR
Broadcast mailbox
Reserved
Split response hit
Futurebus+ CSR address
Reserved
Broadcast CSR address
Reserved
Reserved
Reserved
DPU CSR
Reserved
Reserved
LLLL
LLLH
LLHL
LLHH
LHLL
LHLH
LHHL
LHHH
HLLL
HLLH
HLHL
HLHH
HHLL
HHLH
HHHL
HHHH
Unselected
Memory address compelled
Maximum capable burst or
extended unit space
Memory address 64-byte
burst
32-byte-memory-address
capable
16-byte-memory-address
capable
8-byte-memory-address
capable
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HBADLD*
201
O
TFB2022A DPU
Host address load. Futurebus+ has been granted for the requested transaction out-
put.
HBMASTER*
182
O
TFB2022A DPU
Host master. This device is mastering the host bus transaction.
HMODE < 2:0 >
5, 6, 7
O
TFB2022A DPU
Host mode. HMODE < 2:0 > indicates to the TFB2022A what action is to be taken in
the host interface:
LLL
LLH
LHL
LHH
HLL
HLH
HHL
HHH
Reserved
Between FIFO and host interface (single transfer), between
TFB2022A resident CSR and host interface, or between
TFB2022A resident CSR and FIFO
From FIFO to TFB2022A resident CSR.
Reserved
Reserved
Between FIFO and host interface (burst mode)
Reserved
Reserved
HSTRB*
3
O
TFB2022A DPU
Host strobe. HSTRB* performs next host-interface request as indicated in
HMODE < 2:0 >.
NEWADDR*
21
O
TFB2022A DPU
New address. NEWADDR* increments address in the TFB2022A address register.
SELECTED*
42
O
TFB2022A DPU
Module selected. Futurebus+ transaction uses this module. The DPU is used as a slave
of the Futurebus+ transaction
SPACEAV*
19
I
TFB2022A DPU
Space available in FIFO. In compelled mode, SPACEAV* indicates that space is
available in the FIFO for another transfer. In packet or burst mode, SPACEAV* indicates
that space is available in the FIFO for another packet or burst
UNALIGNED*
202
I
TFB2022A DPU
FB+ slave partial unaligned operation



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