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TIBPLS506ACFN Datasheet(PDF) 3 Page - Texas Instruments |
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TIBPLS506ACFN Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 16 page ![]() 1R 1S C1 1R 1S C1 1R 1S C1 1R 1S C1 1R 1S C1 P5 P6 P7 P8 P9 1R 1S C1 P10 76 1R 1S C1 1R 1S C1 P11 P12 1R 1S C1 P13 1R 1S C1 1 G1 MUX Q0 8 1R 1S C1 1 G1 MUX Q1 9 1R 1S C1 1 G1 MUX Q2 10 1R 1S C1 Q3 11 1R 1S C1 1 G1 MUX Q4 13 1R 1S C1 1 G1 MUX Q5 14 1R 1S C1 1 G1 MUX Q6 15 1R 1S C1 1 G1 MUX Q7 16 80 84 88 92 96 100 104 108 109 10672 10673 10674 10675 10676 10677 10678 10679 1 G1 MUX All inputs to AND gates, exclusive-OR gates, and multiplexers with a blown link assume the logic-1 state. All OR gate inputs with a blown link assume the logic-0 state. |
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