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TMS320DM6433 Datasheet(PDF) 73 Page - Texas Instruments |
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TMS320DM6433 Datasheet(HTML) 73 Page - Texas Instruments |
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73 / 271 page  3.3.1.2 Module Clock State TMS320DM6433 Digital Media Processor www.ti.com SPRS343C – NOVEMBER 2006 – REVISED JUNE 2008 The clock and reset state for each of the modules is controlled by the Power and Sleep Controller (PSC). Table 3-3 shows the default state of each module after a device-level global reset. The DM6433 device has four different module states—Enable, Disable, SyncReset, or SwRstDisable. For more information on the definitions of the module states, the PSC, and PSC programming, see Section 6.3.5, Power and Sleep Controller (PSC) and the TMS320DM643x DMP DSP Subsystem Reference Guide (literature number SPRU978). Table 3-3. DM6433 Default Module States DEFAULT MODULE STATE LPSC # MODULE NAME [PSC Register MDSTATn.STATE] 0 VPSS (Master) SwRstDisable 1 VPSS (Slave) SwRstDisable 2 EDMACC SwRstDisable 3 EDMATC0 SwRstDisable 4 EDMATC1 SwRstDisable 5 EDMATC2 SwRstDisable 6 EMAC Memory Controller SwRstDisable 7 MDIO SwRstDisable 8 EMAC SwRstDisable 9 McASP0 SwRstDisable 11 VLYNQ SwRstDisable 12 HPI SwRstDisable 13 DDR2 Memory Contoller SwRstDisable SwRstDisable, if configuration pins AEM[2:0] = 000b 14 EMIFA Enable, if configuration pins AEM[2:0] = Others [001b, 011b, 100b, and 101b] 15 PCI SwRstDisable 16 McBSP0 SwRstDisable 18 I2C SwRstDisable 19 UART0 SwRstDisable 23 PWM0 SwRstDisable 24 PWM1 SwRstDisable 25 PWM2 SwRstDisable 26 GPIO SwRstDisable 27 TIMER0 SwRstDisable 28 TIMER1 SwRstDisable 39 C64x+ CPU Enable Submit Documentation Feedback Device Configurations 73 |
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