TMS320DM6433 datasheet(81/271 Pages) TI1

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3.4.1.4 Serial Boot Modes (I2C, UART[UART0], SPI[McBSP0])

TMS320DM6433

Digital Media Processor

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SPRS343C – NOVEMBER 2006 – REVISED JUNE 2008

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The C64x+ begins execution from the internal bootloader ROM at address 0x0010 0000.

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Depending on the FASTBOOT, AEM[2:0], and PLLMS[2:0] settings, the bootloader code may

program the PLLC1 to PLL Mode to speed up the boot process. See Table 3-5, Table 3-6, and

Table 3-7.

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The bootloader code reads the code from EMIFA (NAND) EM_CS2 (address 0x4200 0000) using

AIS format.

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EMIFA is configured in NAND mode. The user is responsible for ensuring the desirable

Asynchronous EMIF pins are available through configuration pins AEM[2:0] and AEAW[2:0].

AEM[2:0] can be configured to 001b [8-bit EMIFA (Async) Pinout Mode 1], 011b [8-bit EMIFA

(Async) Pinout Mode 3], 100b [8-bit EMIFA (NAND) Pinout Mode 4], or 101b [8-bit EMIFA (NAND)

Pinout Mode 5]. If AEM[2:0] = 001b, AEAW[2:0] must be configured to 100b.

This subsection discusses how the bootloader configures the clock dividers for the serial boot modes—I2C

boot, UART boot, and SPI boot.

3.4.1.4.1 I2C Boot

If FASTBOOT = 0, then I2C Boot (BOOTMODE = 0101) is performed in Standard-Mode (up-to 100 kbps).

If FASTBOOT = 1, then I2C Boot is performed in Fast-Mode (up-to 400 kbps). The actual I2C data

transfer rate is dependent on the MXI/CLKIN frequency.

This is how the bootloader programs the I2C:

• I2C Boot in Fast-Mode (BOOTMODE[3:0] = 0101b, FASTBOOT = 1)

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I2C register settings: ICPSC.IPSC = 210, ICCLKL.ICCL = 810, ICCKH.ICCH = 810

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Resulting in the following I2C prescaled module clock frequency (internal I2C clock):

• (CLKIN frequency in MHz) / 3

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Resulting in the following I2C serial clock (SCL):

• SCL frequency (in kHz) = (CLKIN frequency in MHz) / 78 * 1000

• SCL low pulse duration (in µs) = 39 / (CLKIN frequency in MHz)

• SCL high pulse duration (in µs) = 39 / (CLKIN frequency in MHz)

• I2C Boot in Standard-Mode (BOOTMODE[3:0] = 0101b, FASTBOOT = 0)

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I2C register settings: ICPSC.IPSC = 210, ICCLKL.ICCL = 4510, ICCKH.ICCH = 4510

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Resulting in the following I2C prescaled module clock frequency (internal I2C clock):

• (CLKIN frequency in MHz) / 3

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Resulting in the following I2C serial clock (SCL):

• SCL frequency (in kHz) = (CLKIN frequency in MHz) / 300 * 1000

• SCL low pulse duration (in µs) = 150 / (CLKIN frequency in MHz)

• SCL high pulse duration (in µs) = 150 / (CLKIN frequency in MHz)

Note: The I2C peripheral requires that the prescaled module clock frequency must be between 7 MHz

and 12 MHz. Therefore, the I2C boot is only available for MXI/CLKIN frequency between 21 MHz and

30 MHz.

For more details on the I2C periperhal configurations and clock requirements, see the TMS320DM643x

DMP Inter-Integrated Circuit (I2C) Peripheral User’s Guide (literature number SPRU991).

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