VON

UVLO

CPVx

CLK

D

Q

Q

Gate

Driver

VON

VOFF

VOFF

DLY

CKVx

CKVBCSx

CKVCSx

CKVBx

R

CS

R

BCS

R

ASG

C

ASG

LCD Panel

R

ASG

C

ASG

B0367-01

DLY

DLY

Delay time

Delay time

C

R

200 k

=

=

W

DLY

10 ms

C

50 nF

47 nF

200 k

=

=

»

W

TPS65191

www.ti.com

SLVS963A – JULY 2009 – REVISED AUGUST 2010

Figure 18. Single-Scan Driver Block Diagram

START-UP SEQUENCE (EN, DLY)

The TPS65191 has an adjustable start-up sequencing that is set by EN and DLY. When VON is below the UVLO

threshold, all outputs are at high impedance. When EN is pulled LOW after UVLO threshold is reached, all

outputs follow VOFF. Pulling EN high enables the device after a delay time set by the capacitor connected to

DLY, and the delay time starts when EN = HIGH. If EN is pulled high before the UVLO threshold is reached, the

delay starts when VON reaches the UVLO threshold. Pulling EN low disables the device, and outputs CKVx,

CKVBx, and STVP follow VOFF as long as VON is higher than the UVLO threshold. For the typical start-up

sequence, see Figure 19 and Figure 20.

SETTING THE DELAY TIME (DLY)

Connecting an external capacitor to the DLY pin sets the delay time. If no delay time is required, the DLY pin can

be left floating. The external capacitor is charged with a constant-current source of typically 15 mA. The delay

time is terminated when the capacitor voltage reaches the internal reference voltage of 2.9 V, and the final DLY

voltage on an external capacitor is maximum 8 V. The voltage rating of the external capacitor must be higher

than 8 V.

The external delay capacitor is calculated using the following formula:

(1)

Example for setting a delay time of 10 ms:

(2)

Copyright © 2009–2010, Texas Instruments Incorporated

Submit Documentation Feedback

13

Product Folder Link(s): TPS65191