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TM4EP64DPN Datasheet(PDF) 29 Page - Texas Instruments |
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TM4EP64DPN Datasheet(HTML) 29 Page - Texas Instruments |
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29 / 43 page  TM2EP64DPN, TM2EP64DJN, TM4EP64DPN, TM4EP64DJN TM2EP72DPN, TM2EP72DJN, TM4EP72DPN, TM4EP72DJN EXTENDEDDATAOUT DYNAMIC RAM MODULES SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) TM2EP64DxN PARAMETER TEST CONDITIONS† ’2EP64DxN-50 ’2EP64DxN-60 ’2EP64DxN-70 UNIT PARAMETER TEST CONDITIONS† MIN MAX MIN MAX MIN MAX UNIT VOH High-level output IOH = − 2 mA LVTTL 2.4 2.4 2.4 V VOH output voltage IOH = − 100 µA LVCMOS VDD −0.2 VDD −0.2 VDD −0.2 V VOL Low-level output IOL = 2 mA LVTTL 0.4 0.4 0.4 V VOL output voltage IOL = 100 µA LVCMOS 0.2 0.2 0.2 V II Input current (leakage) VDD = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VDD ± 10 ± 10 ± 10 µA IO Output current (leakage) VDD = 3.6 V, VO = 0 V to VDD, CASx high ± 10 ± 10 ± 10 µA ICC1‡§ Read- or write-cycle current VDD = 3.6 V, Minimum cycle 960 800 720 mA Standby VIH = 2 V (LVTTL), After one memory cycle, RASx and CASx high 16 16 16 mA ICC2 Standby current VIH = VDD − 0.2 V (LVCMOS), After one memory cycle, RASx and CASx high 8 8 8 mA ICC3‡§ Average refresh current (RAS-only refresh or CBR) VDD = 3.6 V, Minimum cycle, RASx cycling, CASx high (RAS-only refresh), RASx low after CASx low (CBR) 960 800 720 mA ICC4‡¶ Average EDO current VDD = 3.6 V, tHPC = MIN, RASx low, CASx cycling 880 720 640 mA † For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. ‡ Measured with outputs open § Measured with a maximum of one address change while RASx = VIL ¶ Measured with a maximum of one address change during each EDO cycle, tHPC |
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