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SST49LF040 Datasheet(PDF) 22 Page - Silicon Storage Technology, Inc |
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SST49LF040 Datasheet(HTML) 22 Page - Silicon Storage Technology, Inc |
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22 / 48 page ![]() 22 Advance Information 4 Mbit LPC Flash SST49LF040 ©2001 Silicon Storage Technology, Inc. S71213-00-000 11/01 562 TABLE 17: INTERFACE MEASUREMENT CONDITION PARAMETERS Symbol Value Units VTH1 0.6 VDD V VTL1 0.2 VDD V VTEST 0.4 VDD V VMAX1 0.4 VDD V Input Signal Edge Rate 1 V/ns T17.0 562 1. The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met with no more over- drive than this. VMAX specified the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use different voltage values, but must correlate results back to these parameters TABLE 18: STANDARD LPC MEMORY CYCLE DEFINITION (LPC MODE) Field No. of Clocks Description START 1 “0000b” appears on LPC bus to indicate the start of cycle CYCTYPE + DIR 1 Cycle Type: Indicates the type of cycle. Bits 3:2 must be “01b” for memory cycle. Bit 1 indicates the type of transfer “0” for Read, “1” for write. DIR: Indicates the direction of the transfer. “0b” for Read, “1b” for Write. Bit 0 is reserved. “010Xb” indicates memory Read cycle; while “011xb” indicates memory Write cycle. TAR 2 The last component driving LAD[3:0] will drive it to “1111b” during the first clock, and tri- state it during the second clock. ADDR 8 Address Phase for Memory Cycle. LPC supports the 32-bit address protocol. The addresses transfer most significant nibble first and least significant nibble last. (i.e., Address[31:28] on LAD[3:0] first, and Address[3:0] on LAD[3:0] last.) Sync N Synchronize to host or peripheral by adding wait states. “0000b” means Ready, “0101b” means Short Wait, “0110b” means Long Wait, “1001b” for DMA only, “1010b” means error, other values are reserved. The SST49LF040 only supports “Ready” sync. Data 2 Data Phase for Memory Cycle. The data transfer least significant nibble first and most significant nibble last. (i.e., DQ[3:0] on LAD[3:0] first, then DQ[7:4] on LAD[3:0] last.) T18.1 562 |
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