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SST49LF040 Datasheet(PDF) 25 Page - Silicon Storage Technology, Inc

Part # SST49LF040
Description  4 Mbit LPC Flash
PDF  48 Pages
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Manufacturer  SST [Silicon Storage Technology, Inc]
Direct Link  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST49LF040 Datasheet(HTML) 25 Page - Silicon Storage Technology, Inc

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Advance Information
4 Mbit LPC Flash
SST49LF040
25
©2001 Silicon Storage Technology, Inc.
S71213-00-000
11/01 562
FIGURE 13: DATA# POLLING TIMING DIAGRAM (LPC MODE)
562 ILL F12.1
0000b
011Xb
A[11:8]
A[7:4]
A[3:0]
Dn[7:4]
A[15:12]
D[3:0]
Tri-State
TAR
Load Address in 8 Clocks
Write the last command (Program or Erase) to the device in LPC mode.
Address1
1 Clock 1 Clock
1st Start
Memory
Write
Cycle
TAR
Sync
Data
Start next
Command
1 Clock
1 Clock
2 Clocks
Load Data in 2 Clocks
1111b
0000b
0000b
LAD[3:0]
Read the DQ7 to see if internal write complete or not.
LCLK
RST# = VIH
LFRAME#
LAD[3:0]
0000b
010Xb
A[11:8]
A[7:4]
A[3:0]
D7,xxx
A[15:12]
XXXXb
Tri-State
TAR
Load Address in 8 Clocks
When internal write complete, the DQ7 will equal to D7.
Address1
1 Clock 1 Clock
Start
Memory
Read
Cycle
TAR
Sync
Data
Next start
1 Clock
Data out 2 Clocks
1 Clock
2 Clocks
1111b
0000b
0000b
RST# = VIH
LFRAME#
LCLK
0000b
010Xb
A[11:8]
A[7:4]
A[3:0]
D7#,xxx
A[15:12]
XXXXb
Tri-State
TAR
Load Address in 8 Clocks
Address1
1 Clock 1 Clock
Start
Memory
Read
Cycle
TAR
Sync
Data
Next start
1 Clock
Data out 2 Clocks
1 Clock
2 Clocks
1111b
0000b
0000b
CE# = VIL
CE# = VIL
A[23:20]
A[19:16]
A[23:20]
A[19:16]
A[23:20]
A[19:16]
Note: YYYY must be within memory address range specified in Figures 4 and 5.
RST#
LFRAME#
LAD[3:0]
LCLK
CE#
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]



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