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TUSB6010B Datasheet(PDF) 2 Page - Texas Instruments |
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TUSB6010B Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 7 page ![]() www.ti.com Device Power States RESET State IDLE State NORMAL (ACTIVE) State TUSB6010BZQE, TUSB6010BIZQE SLLA269 – OCTOBER 2007 TUSB6010 has three device states typically entered under normal operation: • RESET • IDLE • NORMAL (ACTIVE) The device shall be in RESET state when the RSTn input signal is driven low. In the RESET state: • All output ports are tri-stated or initialized to inactive state • All bi-directional ports are configured as Inputs • All registers are set to their reset value • PHY Macro is enabled and its reference clock output is active Device always enters RESET state asynchronously, but exit the state synchronously. System reset de-assertion is always synchronized with active system clock. Upon asserted system reset, device requires active system clock to exit RESET state. Device enters the IDLE state when External Host sets DevIdle bit in the Device Power Management register. In the IDLE State, the device power consumption should not exceed 100 μA, including companion Power Management device (TPS65030). In IDLE state: • All output signals are driven to state with minimum IO current leakage (pull-up/pull-downs are controllable through Pull-up/Pull-Down Control registers) • All controllable bi-directional pins are placed into minimum current leakage state • All registers and memories retain the content and any read/write registers access is disabled • All clock sources are disabled • PHY Macro is suspended: – Low power VBUS sense comparator is enabled and all regular VBUS comparators are disabled to minimize current consumption. – ID Detection circuitry is enabled – Remaining analog circuitry is disabled Device stays in the IDLE state until a valid wake-up event occurs and transitions into the NORMAL (ACTIVE) State. If system reset is asserted (RSTn) device transitions to RESET state. A transition to the Normal state is required for normal device operation. All circuitry is enabled. In the Normal state: • All I/O are enabled. • All registers and memories are accessible • Clock sources are enabled • PHY Macro is enabled – Session End VBUS detect circuitry shall be enabled – VBUS detection circuitry shall be enabled – ID Detection circuitry shall enabled 2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TUSB6010BZQE, TUSB6010BIZQE |
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