SN74ALS235

64 × 5 ASYNCHRONOUS FIRST IN, FIRST OUT MEMORY

SDAS108A − OCTOBER 1986 − REVISED SEPTEMBER 1993

5

POST OFFICE BOX 655303

POST OFFICE BOX 1443

logic diagram (positive logic) (continued)

Word 3

Word 2

Word 7

Word 8

Word 9

Word 10

Data

Outputs

Word 1

Q1

Q2

Q3

OR

Q0

HF

AF/AE

IR

1

2

3

4

5

6

7

timing diagram

Shift In

W1

RST

IR

OR

AF/AE

HF

Clear

Almost

Empty+1

Empty

Full

Half

Full

Almost

Full

Word 1

SI

D4 − D0

SO

Q4 − Q0

W2

W8

W31

W32

W55 W56

Don’t Care

W1

W1

W63

W64

W1

Word 2

Word 55

Word 56

Invalid†

Word 1‡

Word 2

Word3

W1

W9

† The last data word shifted out of the FIFO remains at the output until a new word falls through or a RST pulse clears the FIFO.

‡ While the output data is considered valid only when the OR flag is high, the stored data remains at the output. Any additional words written into

the FIFO will stack up behind the first word and will not appear at the output until SO is taken low.