MSP430G22x0

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SLAS753D – JANUARY 2012 – REVISED AUGUST 2012

TERMINAL

NO.

DESCRIPTION

NAME

I/O

D

P1.2/

General-purpose digital I/O pin

2

I/O

TA0.1/

Timer_A, capture: CCI1A input, compare Out1 output

A2

ADC10 analog input A2

P1.5/

General-purpose digital I/O pin

TA0.0/

Timer_A, compare Out0 output

3

I/O

A5/

ADC10 analog input A5

SCLK

USI: clock input in I2C mode; clock input/output in SPI mode

P1.6/

General-purpose digital I/O pin

TA0.1/

Timer_A, capture: CCI1B input, compare: Out1 output

4

I/O

A6/

ADC10 analog input A6

SDO/

USI: Data output in SPI mode

SCL

USI: I2C clock in I2C mode

P1.7/

General-purpose digital I/O pin

A7/

ADC10 analog input A7

5

I/O

SDI/

USI: Data input in SPI mode

SDA

USI: Data input in I2C mode

RST/

Reset input

6

I

NMI/

Nonmaskable interrupt input

SBWTDIO

Spy-Bi-Wire test data input/output during programming and test

TEST/

Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.

7

I

SBWTCK

Spy-Bi-Wire test clock input during programming and test

DVCC

1

Digital supply voltage

DVSS

8

Digital ground reference

(1)

The GPIOs P1.0, P1.1, P1.3, P1.4, P2.6, and P2.7 are implemented but not available on the device pinout. To avoid floating inputs,

these digital I/Os should be properly configured. The pullup or pulldown resistors of the unbounded P1.x GPIOs should be enabled, and

the VLO should be selected as the ACLK source (see the MSP430x2xx Family User's Guide (SLAU144)).

Copyright © 2012, Texas Instruments Incorporated

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