MSP430G22x0

SLAS753D – JANUARY 2012 – REVISED AUGUST 2012

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TERMINAL

NO.

DESCRIPTION

NAME

I/O

D

P1.2/

General-purpose digital I/O pin

2

I/O

TA0.1/

Timer_A, capture: CCI1A input, compare Out1 output

CA2

Comparator_A+, CA2 input

P1.5/

General-purpose digital I/O pin

3

I/O

TA0.0/

Timer_A, compare Out0 output

CA5

Comparator_A+, CA5 input

P1.6/

General-purpose digital I/O pin

4

I/O

TA0.1/

Timer_A, compare: Out1 output

CA6

Comparator_A+, CA6 input

P1.7/

General-purpose digital I/O pin

5

I/O

CAOUT/

Comparator_A+, output

CA7

Comparator_A+, CA7 input

RST/

Reset input

6

I

NMI/

Nonmaskable interrupt input

SBWTDIO

Spy-Bi-Wire test data input/output during programming and test

TEST/

Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.

7

I

SBWTCK

Spy-Bi-Wire test clock input during programming and test

DVCC

1

Digital supply voltage

DVSS

8

Digital ground reference

(1)

The GPIOs P1.0, P1.1, P1.3, P1.4, P2.6, and P2.7 are implemented but not available on the device pinout. To avoid floating inputs,

these digital I/Os should be properly configured. The pullup or pulldown resistors of the unbounded P1.x GPIOs should be enabled, and

the VLO should be selected as the ACLK source (see the MSP430x2xx Family User's Guide (SLAU144)).

4

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