UM10406

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© NXP B.V. 2010. All rights reserved.

User manual

Rev. 01 — 3 August 2010

6 of 21

NXP Semiconductors

UM10406

SSL1523 5 W LED driver

The input circuit of the converter must be equipped with a filter that is partially capacitive,

in order to address the EMC requirements (see Figure 5). The combination of C1, L1 and

C2 make a filter that blocks most of the disturbance generated by the converter input

current. This filter is designed to have a limited capacitive load, so a good power factor

can be achieved. For this design, two 150 nF capacitors are incorporated, resulting in a

power factor of at least 0.9 for the nominal condition with six LEDs connected at 5 W

output power.

The board is equipped with a feedback loop to regulate the output current. This feedback

loop senses the LED current over sense resistor R10, and a current mirror is made from

transistors Q10a/Q10b. Using R18, the current level can then be set. The same feedback

loop is also used to provide overvoltage protection. If the LED voltage exceeds 33 V, a

current through R17 and D11, D12 and D13 will start running. The current through the

opto coupler IC2 will pull up the REG pin. At values above 2.7 V, the ‘on time’ of the

internal MOSFET is zero. The feedback loop has a proportional, and partially integrated

action. The gain is critical due to the phase shift caused by the converter and the output

capacitor C10. Increased gain will make the feedback loop intrinsically unstable.

The accuracy of the resulting output current will satisfy the requirements of the majority of

the 5 W LED applications with four to eight LEDs connected in series. The demo board

can be controlled by connecting the floating output of an external opto coupler (TCDT1124

or equivalent) to K4.

The demo board can be switched on and off by switching the external opto coupler.

Controlling the LED current is another option. The LED current can be regulated by

applying a PWM signal to the external input with a frequency up to 1 kHz. The PWM

frequency can be synchronized with the ripple frequency on the buffer capacitor C1 for an

optimal mains input current shape.

Fig 4.

019aaa135