M24128-DF datasheet(30/40 Pages) STMICROELECTRONICS

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DC and AC parameters

M24128-BW M24128-BR M24128-BF M24128-DF

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Doc ID 16892 Rev 21

Table 17.

1 MHz AC characteristics

Symbol

Alt.

Parameter(1)

Only for M24128 devices identified by the process letter K.

Min.

Max.

Unit

fSCL

Clock frequency

MHz

tCHCL

tHIGH

Clock pulse width high

260

tCLCH

tLOW

Clock pulse width low

500

tXH1XH2

Input signal rise time

(2)

There is no min. or max. values for the input signal rise and fall times. It is however recommended by the

I²C specification that the input signal rise and fall times be less than 120 ns when fC <1MHz.

(2)

tXL1XL2

Input signal fall time

(2)

tQL1QL2

(3)

Characterized only, not tested in production.

SDA (out) fall time

20(4)

With CL = 10 pF.

120

tDXCX

tSU:DAT Data in setup time

tCLDX

tHD:DAT Data in hold time

tCLQX

(5)

To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or

rising edge of SDA.

tDH

Data out hold time

100

tCLQV

(6)

tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or

0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 13.

tAA

Clock low to next data valid (access time)

450

tCHDL

tSU:STA Start condition setup time

250

tDLCL

tHD:STA Start condition hold time

250

tCHDH

tSU:STO Stop condition setup time

250

tDHDL

tBUF

Time between Stop condition and next Start

condition

500

tWLDL

(7)(3)

WC=0 set up time condition to enable the execution of a WRITE command.

tSU:WC WC set up time (before the Start condition)

µs

tDHWH

(8)(3)

WC=0 hold time condition to enable the execution of a WRITE command.

tHD:WC WC hold time (after the Stop condition)

µs

tWR

Write time

tNS

(3)

Pulse width ignored (input filter on SCL and

SDA)

-80

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