CXP-85232A datasheet(16/20 Pages) SONY

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CXP85112B/85116B, CXP85220A/85224A/85228A/85232A

(6) I2C bus timing

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item

SCL clock frequency

Bus free time prior to transfer start

Transfer start hold time

Clock Low level width

Clock High level width

Setup time during repetitive transfer

Data hold time

Data setup time

SDA, SCL rise time

SDA, SCL fall time

Transfer end setup time

fSLC

tBUF

tHD; STA

tLOW

tHIGH

tSU; STA

tHD; DAT

tSU; DAT

tSU; STO

SCL

SDA, SCL

SCL

SDA, SCL

4.7

4.0

4.7

4.0

4.7

0∗1

250

4.7

100

300

kHz

µs

Symbol

Pins

Conditions

Min.

Max.

Unit

∗1 The data hold time does not take into consideration SCL rise time (300ns max.). Ensure that the data hold

time exceeds 300ns.

Fig. 9. I2C bus transfer timing

tSU; STO

tSU; STA

tHD; STA

tSU; DAT

tHIGH

tHD; DAT

tLOW

tHD; STA

tBUF

SDA

SCL

Fig. 10. Recommended circuit example for I2C device

I2C device

RS RS

RS RP

SDA0

(or SDA1)

SCL0

(or SCL1)

• Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).

• Serial resistance (Rs = 300

Ω and under) of SDA0 (or SDA1) and SCL0 (or SCL1) reduces spike noise

caused by CRT flashover.

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