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CXP-85232A Datasheet(PDF) 17 Page - Sony Corporation |
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CXP-85232A Datasheet(HTML) 17 Page - Sony Corporation |
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17 / 20 page ![]() – 17 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (7) OSD (On-Screen Display) timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item OSD clock frequency HSYNC pulse width VSYNC pulse width HSYNC after-edge rise time/fall time VSYNC after-edge rise time/fall time fOSC tHWD tVWD tHCG tVCG EXLC XLC HSYNC VSYNC HSYNC VSYNC Fig. 12 Fig. 11 Fig. 11 Fig. 11 Fig. 11 4 1.2 1.0 13 200 1.0 MHz µs H* ns µs Symbol Pins Condition Unit Min. Max. Fig. 11. OSC timing 0.8VDD 0.2VDD tHCG tHWD HSYNC when Bit 5 of OPOL register (01FBH) is set to "0" 0.8VDD 0.2VDD tVCG VSYNC when Bit 4 of OPOL register (01FBH) is set to "0" tVWD Fig. 12. LC oscillation circuit example L C2 C1 EXLC XLC * H indicates 1HSYNC period. |
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