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WM8533 Datasheet(PDF) 17 Page - Wolfson Microelectronics plc |
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WM8533 Datasheet(HTML) 17 Page - Wolfson Microelectronics plc |
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17 / 41 page ![]() Production Data WM8533 w PD, July 2012, Rev 4.0 17 Figure 10 Single Register Write to Specified Address Figure 11 Single Register Read from Specified Address SPI CONTROL MODE The WM8533 can also be controlled by writing to registers through a SPI control interface. A control word consists of 24 bits. The first bit is the read/write bit (R/W ¯¯) which must always be 0, which is followed by 7 address bits (A6 to A0) that determine which control register is accessed. The remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in each control register. Volume update registers R06h and R07h are unavailable in SPI control mode. To use volume update in software control mode, I 2C mode must be used. In SPI mode, every rising edge of SCLK clocks in one data bit from the SDA pin. A rising edge on CS ¯¯ latches in a complete control word consisting of the last 24 bits. The SPI mode write operation protocol is illustrated in Figure 12. Figure 12 SPI Control Interface – Write operation In Write operations (R/W ¯¯=0), all SDA bits are driven by the controlling device. |
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