WM8215 datasheet(26/31 Pages) WOLFSON

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WM8215

Production Data

PD, Rev 4.3, September 2012

ADDRESS

<A5:A0>

BIT

NAME(S)

DEFAULT

DESCRIPTION

ACYC

When LINEBYLINE = 0 this bit has no effect.

When LINEBYLINE = 1 this bit determines the function of

the RSMP input pin and the offset/gain register controls.

0 = RSMP pin enabled for either reset sampling (CDS) or

Reset Level Clamp control. Internal selection of gain/offset

multiplexers using INTM[1:0] register bits.

1 = Auto-cycling enabled by pulsing the RSMP input pin.

This means that each time a pulse is applied to this pin the

single input channel will switch to the next offset register

and gain register in the sequence. The sequence is

Red->Green->Blue->Red… offset and gain registers

applied to the red input channel.

When auto-cycling is enabled, the RSMP pin alone cannot

be used to control reset level clamping. Reset level

clamping may be enabled in this situation by setting the

CLAMPCTRL and RLCEN bits so that he logical AND of

RSMP and VSMP closes the clamp switch.

When auto-cycling is enabled, the RSMP pin cannot be

used for reset sampling (i.e. CDS must be set to 0).

3:2

INTM[1:0]

When LINEBYLINE=0 or ACYC=1 this bit has no effect.

When LINEBYLINE=1 and ACYC=0:

Controls the PGA/offset mux selector:

00 = Red PGA/Offset registers applied to input channel

01 = Green PGA/Offset registers applied to input channel

10 = Blue PGA/Offset registers applied to input channel

11 = Reserved.

7:4

Reserved

0000

Must be set to 0

000111

(07h)

Setup Register

REDPD

When set powers down red S/H, PGA

GRNPD

When set powers down green S/H, PGA

BLUPD

When set powers down blue S/H, PGA

ADCPD

When set powers down ADC. Allows reduced power

consumption without powering down the references which

have a long time constant when switching on/off due to the

external decoupling capacitors.

VRLCDACPD

When set powers down 4-bit RLCDAC, setting the output to

a high impedance state and allowing an external reference

to be driven in on the VRLC/VBIAS pin.

ADCREFPD

When set disables VRT, VRB buffers to allow external

references to be used.

VRXPD

When set disables VRX buffer to allow an external

reference to be used.

Not Used

Must be set to 0

001000

(08h)

Setup Register

4:0

Not Used

00000

Must be set to 0

RLCEN

Reset Level Clamp Enable. When set Reset Level

Clamping is enabled. The method of clamping is

determined by CLAMPCTRL.

CLAMPCTRL

0 = RLC switch is controlled directly from RSMP input pin:

RSMP = 0: switch is open

RMSP = 1: switch is closed

1 = RLC switch is controlled by logical combination of

RSMP and VSMP.

RSMP && VSMP = 0: switch is open

RSMP && VSMP = 1: switch is closed

Reserved

Must be set to 0

WM8215 Datasheet(PDF) 26 Page - Wolfson Microelectronics plc

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