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RT9625B Datasheet(PDF) 13 Page - Richtek Technology Corporation |
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RT9625B Datasheet(HTML) 13 Page - Richtek Technology Corporation |
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13 / 14 page ![]() RT9625B 13 DS9625B-02 September 2012 www.richtek.com © Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Layout Consideration Figure 6 shows the schematic circuit of a synchronous buck converter to implement the RT9625B. The converter operates from 5V to 12V of input Voltage. For the PCB layout, it should be very careful. The power circuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The location of QUGx, QLGx, Lx should be very close. Next, the trace from UGATEx, and LGATEx should also be short to decrease the noise of the driver output signals. PHASEx signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor CVCC should be connected to GND directly. Furthermore, the bootstrap capacitors (CBOOTx) should always be placed as close to the pins of the IC as possible. Figure 6. Synchronous Buck Converter Circuit Figure 5. Derating Curve of Maximum Power Dissipation 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 25 50 75 100 125 Ambient Temperature (°C) Four-Layer PCB Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJAis the junction to ambient thermal resistance. For recommended operating condition specifications of the RT9625B, the maximum junction temperature is 125 °C. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN-16L 4x4 packages, the thermal resistance, θJA, is 54°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA= 25 °C can be calculated by the following formula : PD(MAX) = (125 °C - 25°C) / (54°C/W) = 1.852W for WQFN-16L 4x4 package The maximum power dissipation depends on the operating ambient temperature for fixed TJ(MAX) and thermal resistance, θJA. The derating curve in Figure 5 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. BOOTx UGATEx PHASEx LGATEx VCC RT9625B GND CBOOTx 12V LIN COUT VIN VOUT CIN2 PHB83N03LT PHB95N03LT Lx QLGx QUGx CIN 12V PWMx PWMx CVCC RVCC |
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