AD1845

–27–

REV. C

Power-Down Control Register (IXA3:0 = 27)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

27

ADCPWD

DACPWD

MIXPWD

res

FREN

res

res

res

res

Reserved for future expansion. Always write zeros to these bits.

FREN

Frequency Select Register Enable. In MODE2, selecting this bit will turn on the Frequency Select Registers (see

indirect registers 22 and 23) and disable CFS2:0.

0

CFS Active.

1

Frequency Select Registers Active, CFS disabled.

MIXPWD

Mixer Power Down. The DAC and the output mixer are powered down, and the DAC sample clock is turned off.

DACPWD

DAC Power Down. The DAC is powered down and the DAC sample clock is turned off.

ADCPWD

ADC Power Down. The ADC is powered down and the ADC sample clock is turned off.

This register’s initial state after reset is “000x 0xxx.”

Capture Data Format Control Register (IXA3:0 = 28)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

28

CFMT1

CFMT0

CC/L

CS/M

res

res

res

res

NOTE: Changing CFMT[1:0], CC/L, CS/M, requires the Mode Change Enable (MCE) state or setting CEN = 0.

res

Reserved for future expansion. Always write zeros to these bits.

CS/M

Capture Stereo/Mono Select. Setting this bit determines how the captured audio data will be formatted. In the

Mono mode, valid information is captured on the “left” channel, and the “right” channel data is not valid.

0

Mono Format

1

Stereo Format

CC/L

Capture Companding/Linear Select. This bit is set to determine linear,

µ-Law or A-Law companding. See Figure

12 for CFMT[1:0] and CC/L bit settings that determine the audio data type capture format.

CFMT[1:0]

Capture Data Format. This bit is set to format the data being captured in MODE 2. See Figure 12 for CFMT

and CC/L bit settings that determine the capture audio data type format.

This register’s initial state after reset is “0000 xxxx.”

CFMT1

CFMT0

CC/L

Audio Data Type

0

0

0

Linear, 8-Bit Unsigned PCM

00

1

µ-Law, 8-Bit Companded

0

1

0

Linear, 16-Bit Twos Complement PCM Little Endian

0

1

1

A-Law, 8-Bit Companded

1

0

0

Reserved

1

0

1

Reserved

1

1

0

Linear, 16-Bit Twos-Complement Big Endian

1

1

1

Reserved

Figure 12. Capture Audio Data Type

Crystal, Clock Select/Total Power-Down Register (IXA3:0 = 29)

IXA3:0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

29

XFS2

XFS1

XFS0

res

res

res

res

TOTPWD

TOTPWD

Total Power Down. When TOTPWD = HI, the ADC, DAC, mixer, and voltage reference are powered down, and

the ADC and DAC sample clocks are turned off. Only the digital interface remains active to allow the host to exit

the AD1845 from the total power-down state.

res

Reserved for future expansion. Always write zeros to these bits.