AD1847

REV. B

–12–

Index Readback (16-Bit)

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

CLOR

MCE

RREQ

res

IA3

IA2

IA1

IA0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

DATA7:0 Index Register Data. These bits are the readback data from the desired AD1847 Index Register referenced by the Index

Address from the previous Control Word (with the RREQ bit set). Read by the host CPU or DSP from the AD1847.

IA3:0

Index Register Address. These bits echo the indirect address (written during the previous Control Word (with the RREQ

bit set) of the desired AD1847 Index Register to be readback. Read by the host CPU or DSP from the AD1847.

RREQ

Read Request. This bit is set HI for Index Readback, echoing the RREQ state written by the host CPU or DSP in the

previous Control Word. Read by the host CPU or DSP from the AD1847.

res

Reserved for future expansion. All reserved bits read zero (LO).

MCE

Mode Change Enable. This bit echoes the MCE state written by the host CPU or DSP during the previous* Control

Word (with the RREQ bit set). Read by the host CPU or DSP from the AD1847.

CLOR

Clear Overrange. This bit echoes the CLOR state written by the host CPU or DSP during the previous Control Word

(with the RREQ bit set). Read by the host CPU or DSP from the AD1847.

Immediately after reset, the contents of this register is: 1110 0000 0000 0000 (E000h).

Indirect Mapped Registers

Following in Figure 6 is a table defining the mapping of AD1847 8-bit Index Registers to Index Address. These registers are accessed

by writing the appropriate 4-bit Index Address in the Control Word.

Index

Register Name

0

Left Input Control

1

Right Input Control

2

Left Aux #1 Input Control

3

Right Aux #l Input Control

4

Left Aux #2 Input Control

5

Right Aux #2 Input Control

6

Left DAC Control

7

Right DAC Control

8

Data Format

9

Interface Configuration

1 0

Pin Control

1 1

Invalid Address

1 2

Miscellaneous Information

1 3

Digital Mix Control

1 4

Invalid Address

1 5

Invalid Address

Figure 6. Index Register Mapping

A detailed description of each of the Index Registers is given below.