AD1877

REV. A

–14–

BCLK

RDEDGE = LO

BCLK

RDEDGE = HI

31

32

1

2

3

4

16

SOUT

OUTPUT

WCLK

OUTPUT

TAG

OUTPUT

LSB

LEFT TAG

LSB

RIGHT TAG

31

32

1

2

3

4

16

MSB-1

LEFT DATA

MSB-2

LSB

MSB

MSB-1

RIGHT DATA

MSB-2

LSB

ZEROS

ZEROS

ZEROS

INPUT

L

RCK

INPUT

17

18

17

18

MSB

MSB

MSB

Figure 9. Serial Data Output Timing: Slave Mode, Left-Justified with No MSB Delay, S/

M = Hl,

R

LJUST = LO, MSBDLY = Hl

BCLK

RDEDGE = LO

BCLK

RDEDGE = HI

32

1

2

3

4

17

SOUT

OUTPUT

WCLK

OUTPUT

TAG

OUTPUT

MSB

LEFT TAG

MSB

RIGHT TAG

31

32

1

2

3

4

17

MSB-1

LEFT DATA

MSB-2

LSB

MSB-1

RIGHT DATA

MSB-2

LSB

ZEROS

ZEROS

ZEROS

INPUT

L

RCK

INPUT

5

5

MSB

LSB

MSB

LSB

M = Hl, RLJUST = LO, MSBDLY = LO

BCLK

RDEDGE = LO

BCLK

RDEDGE = HI

31

32

1

2

15

16

17

18

19

32

1

2

15

16

17

18

19

32

1

2

MSB-14

LSB

PREVIOUS DATA

MSB-1

LEFT DATA

MSB-2

LSB

RIGHT DATA

SOUT

OUTPUT

ZEROS

ZEROS

MSB-1 MSB-2

LSB

ZEROS

WCLK

OUTPUT

TAG

OUTPUT

MSB

LSB

LEFT TAG

MSB

LSB

RIGHT TAG

MSB

LSB

LEFT TAG

OUTPUT

L

RCK

OUTPUT

MSB

MSB

Figure 11. Serial Data Output Timing: Master Mode, Right-Justified with No MSB Delay, S/

M = LO,

R

LJUST = Hl, MSBDLY = Hl