REV. 0

AD1887

–12–

General Purpose Register (Index 20h)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

h

0

2h

0

2 h

0

2 h

0

2h

0

2e

s

o

p

r

u

P

l

a

r

e

n

e

Ge

s

o

p

r

u

P

l

a

r

e

n

e

G

e

s

o

p

r

u

P

l

a

r

e

n

e

G

e

s

o

p

r

u

P

l

a

r

e

n

e

Ge

s

o

p

r

u

P

l

a

r

e

n

e

GX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XK

B

P

LK

B

P

L

K

B

P

L

K

B

P

LK

B

P

LX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

Xh

0

0

0

0h

0

0

0

0

h

0

0

0

0

h

0

0

0

0h

0

0

0

0

Note: This register should be read before writing to generate a mask for only the bit(s) that need to be changed. The function default

value is 0000h, which is all off.

LPBK

Loopback Control. ADC/DAC digital loopback mode.

Subsection Ready Register (Index 26h)

g

e

Rg

e

R g

e

R g

e

Rg

e

R

m

u

Nm

u

N m

u

N m

u

Nm

u

N

e

m

a

Ne

m

a

N

e

m

a

N

e

m

a

Ne

m

a

N5

1

D5

1

D 5

1

D 5

1

D5

1

D4

1

D4

1

D 4

1

D 4

1

D4

1

D3

1

D3

1

D 3

1

D 3

1

D3

1

D2

1

D2

1

D 2

1

D 2

1

D2

1

D1

1

D1

1

D 1

1

D 1

1

D1

1

D0

1

D0

1

D 0

1

D 0

1

D0

1

D9

D9

D9

D9

D9

D8

D8

D8

D8

D8

D7

D7

D7

D7

D7

D6

D6

D6

D6

D6

D5

D5

D5

D5

D5

D4

D4

D4

D4

D4

D3

D3

D3

D3

D3

D2

D2

D2

D2

D2

D1

D1

D1

D1

D1

D0

D0

D0

D0

D0

Dt

l

u

a

f

e

Dt

l

u

a

f

e

D

t

l

u

a

f

e

D

t

l

u

a

f

e

Dt

l

u

a

f

e

D

h

6

2h

6

2 h

6

2 h

6

2h

6

2t

a

t

S

/

l

r

t

n

C

n

w

o

D

-

r

e

w

o

Pt

a

t

S

/

l

r

t

n

C

n

w

o

D

-

r

e

w

o

P

t

a

t

S

/

l

r

t

n

C

n

w

o

D

-

r

e

w

o

P

t

a

t

S

/

l

r

t

n

C

n

w

o

D

-

r

e

w

o

Pt

a

t

S

/

l

r

t

n

C

n

w

o

D

-

r

e

w

o

PX

X

X

X

X6

R

P6

R

P 6

R

P 6

R

P6

R

P5

R

P5

R

P 5

R

P 5

R

P5

R

P4

R

P4

R

P 4

R

P 4

R

P4

R

P3

R

P3

R

P 3

R

P 3

R

P3

R

P2

R

P2

R

P 2

R

P 2

R

P2

R

P1

R

P1

R

P 1

R

P 1

R

P1

R

P0

R

P0

R

P 0

R

P 0

R

P0

R

PX

X

X

X

XX

X

X

X

XX

X

X

X

XX

X

X

X

XF

E

RF

E

R F

E

R F

E

RF

E

RL

N

AL

N

A L

N

A L

N

AL

N

AC

A

DC

A

D C

A

D C

A

DC

A

DC

D

AC

D

A C

D

A C

D

AC

D

AA

NA

NA

NA

NA

N

Note: The ready bits are read only, writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the

AD1887 subsections. If the bit is a one, that subsection is “ready.” Ready is defined as the subsection able to perform in its nomi-

nal state.

ADC

ADC section ready to transmit data.

DAC

DAC section ready to accept data.

ANL

Analog gainuators, attenuators, and mixers ready.

REF

PR[5:0]

AD1887 Power-Down Modes. The first three bits are to be used individually rather than in combination with each

other. The last bit, PR3, can be used in combination with PR2 or by itself. The mixer and reference cannot be

powered down via PR3 unless the ADCs and DACs are also powered down. Nothing else can be powered up until

the reference is up.

PR0 – Powered-Down ADC

PR1 – Powered-Down DAC

PR2 – Powered-Down Analog Mixer

PR4 – Powered-Down AC-Link

PR5 – Powered-Down Internal Clock

PR6 – Powered-Down Headphone

PR5 has no effect unless all ADCs, DACs, and the AC-Link are powered down. The reference and the mixer can

be either up or down, but all power-up sequences must be allowed to run to completion before PR5 and PR4 are

both set.

In multiple-codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also effective in

the slave codec if the master’s PR5 bit is clear, but the PR4 bit has no effect or disable PR5.

Power-Down State

PR6

PR5

PR4

PR3

PR2

PR1

PR0

ADC Power-Down

0000001

DACs Power-Down

0000010

ADC and DAC Power-Down

0000011

Mixer Power-Down

0000100

ADC + Mixer Power-Down

0000101

DAC + Mixer Power-Down

0000110

ADC + DAC + Mixer Power-Down

0000111

Standby

1111111