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PRELIMINARY TECHNICAL DATA

AD5280/AD5282

REV PrE 12 MAR 02

Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final

product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com

ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (V

DD = +5V, VSS = -5V, VLOGIC = +5V,

VA = +VDD, VB = 0V, -40°C < TA < +85°C unless otherwise noted.)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

DYNAMIC CHARACTERISTICS6,9,11

Bandwidth –3dB

BW_20K

RAB = 20K

Ω, Code = 80H

650

kHz

BW_50K

RAB = 50K

Ω, Code = 80H

142

kHz

BW_200K

RAB = 200K

Ω, Code = 80H

kHz

Total Harmonic Distortion

THDW

VA =1Vrms + 2V dc, VB = 2V DC, f=1KHz

0.005

VW Settling Time

VA= VDD, VB=0V, ±1 LSB error band

µs

Resistor Noise Voltage

eN_WB

RWB = 10KΩ, f = 1KHz

√Hz

INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)

SCL Clock Frequency

fSCL

400

KHz

tBUF Bus free time between STOP & START

1.3

µs

tHD;STA Hold Time (repeated START)

After this period the first clock pulse is generated

0.6

µs

tLOW Low Period of SCL Clock

1.3

µs

tHIGH High Period of SCL Clock

0.6

µs

tSU;STA Setup Time For START Condition t5

0.6

µs

tHD;DAT Data Hold Time

0.9

µs

tSU;DAT Data Setup Time

100

tF Fall Time of both SDA & SCL signals

300

tR Rise Time of both SDA & SCL signals

300

tSU;STO Setup time for STOP Condition

t10

0.6

µs

NOTES:

Typicals represent average readings at +25°C, VDD = +5V, VSS = -5V.

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the

relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

VAB = VDD, Wiper (VW) = No connect

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V.

DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.

Resistor terminals A,B,W have no limitations on polarity with respect to each other.

Guaranteed by design and not subject to production test.

Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value

result in the minimum overall power consumption.

10.

PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation.

11.

All dynamic characteristics use VDD = +5V.

12.

See timing diagram for location of measured values.

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