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AD5330/AD5331/AD5340/AD5341

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Bipolar Operation Using the AD5330/AD5331/AD5340/AD5341

The AD5330/AD5331/AD5340/AD5341 have been designed

for single supply operation, but bipolar operation is achievable

using the circuit shown in Figure 36. The circuit shown has been

conﬁgured to achieve an output voltage range of –5 V < VO <

+5 V. Rail-to-rail operation at the ampliﬁer output is achievable

using an AD820 or OP295 as the output ampliﬁer.

The output voltage for any input code can be calculated as

follows:

VO = [(1 + R4/R3)

× (R2/(R1 + R2) × (2 × VREF × D/2

N)] – R4 × V

REF/R3

where:

D is the decimal equivalent of the code loaded to the DAC, N is

DAC resolution and VREF is the reference voltage input.

With:

VREF = 2.5 V

R1 = R3 = 10 k

Ω

R2 = R4 = 20 k

Ω and VDD = 5 V.

VOUT = (10

× D/2N) – 5

AD5330/AD5331/

AD5340/AD5341

GND

VDD = 5V

EXT

REF

VOUT

AD780/REF192

WITH VDD = 5V

AD589 WITH VDD = 2.5V

GND

VIN

VOUT

VREF

VDD

10k

20k

+5V

–5V

0.1 F

10 F

Figure 36. Bipolar Operation using the AD5330/AD5331/

AD5340/AD5341

Decoding Multiple AD5330/AD5331/AD5340/AD5341

The

CS pin on these devices can be used in applications to decode

a number of DACs. In this application, all DACs in the system

receive the same data and

WR pulses, but only the CS to one of

the DACs will be active at any one time, so data will only be

written to the DAC whose

CS is low. If multiple AD5341s are

being used, a common HBEN line will also be required to

determine if the data is written to the high-byte or low-byte

The 74HC139 is used as a 2- to 4-line decoder to address any

of the DACs in the system. To prevent timing errors, the enable

input should be brought to its inactive state while the coded

address inputs are changing state. Figure 37 shows a diagram of a

typical setup for decoding multiple devices in a system. Once

data has been written sequentially to all DACs in a system, all the

DACs can be updated simultaneously using a common

LDAC

line. A common

CLR line can also be used to reset all DAC

outputs to zero.

ENABLE

CODED

ADDRESS

VDD

VCC

74HC139

DGND

1Y0

1Y1

1Y2

1Y3

HBEN

LDAC

CLR

DATA

INPUTS

DATA

INPUTS

DATA

INPUTS

DATA

INPUTS

*AD5341 ONLY

HBEN*

LDAC

CLR

AD5330/AD5331/

AD5340/AD5341

HBEN*

LDAC

CLR

HBEN*

LDAC

CLR

HBEN*

LDAC

CLR

AD5330/AD5331/

AD5340/AD5341

AD5330/AD5331/

AD5340/AD5341

AD5330/AD5331/

AD5340/AD5341

Figure 37. Decoding Multiple DAC Devices

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