REV. 0

AD5532

–11–

FUNCTIONAL DESCRIPTION

The AD5532 can be thought of as consisting of 32 DACs and

an ADC (for SHA mode) in a single package. In DAC mode a

14-bit digital word is loaded into one of the 32 DAC registers

via the serial interface. This is then converted (with gain and

To update a DAC’s output voltage the required DAC is addressed

via the serial port. When the DAC address and code have been

loaded the selected DAC converts the code.

On power-on, all the DACs, including the offset channel, are

loaded with zeros. The internal DAC outputs are at 50 mV

typical (negative full-scale). If the OFFS_IN pin is driven by

(Gain

× V

× V

Output Buffer Stage—Gain and Offset

The function of the output buffer stage is to translate the 0 V–3 V

output of the DAC to a wider range. This is done by gaining up

the DAC output by 3.52/7 and offsetting the voltage by the

voltage on OFFS_IN pin.

AD5532-1/AD5532-3/AD5532-5:

AD5532-2:

to the offset voltage supplied by the user:

Table I. Sample Output Voltage Ranges

(V)

(V)

(AD5532-1/-3/-5)

(AD5532-2)

0.5

0 to 3

–1.26 to +9.3

Headroom Limited

1

0 to 3

–2.52 to +8.04

–6 to +15

Offset Voltage Channel

The offset voltage can be externally supplied by the user at

OFFS_IN or it can be supplied by an additional offset volt-

age channel on the device itself. The offset can be set up in

two ways. In SHA mode the required offset voltage is set up

code corresponding to the offset value is loaded directly into

the offset DAC. This offset channel’s DAC output is directly

connected to OFFS_OUT. By connecting OFFS_OUT to OFFS_IN

this offset voltage can be used as the offset voltage for the 32

output amplifiers. It is important to choose the offset so that

Reset Function

The reset function on the AD5532 can be used to reset all nodes

on this device to their power-on-reset condition. This is imple-

mented by applying a low-going pulse of between 50 ns and 150 ns

to the

TRACK/RESET pin on the device. If the applied pulse is

less than 50 ns it is assumed to be a glitch and no operation

takes place. If the applied pulse is wider than 150 ns this pin

to the output buffer and an acquisition on the channel will not

occur until a rising edge of

TRACK.

SHA Mode

into a digital word. The noninverting input to the output buffer

to avoid spurious outputs while the DAC acquires the correct

code. This is completed in 16

µs max. At this time the updated

DAC output assumes control of the output voltage. The output

voltage of the DAC is connected to the noninverting input of

the output buffer. Since the channel output voltage is effectively

the output of a DAC there is no droop associated with it. As

long as power is maintained to the device the output voltage will

remain constant until this channel is addressed again.

Analog Input (SHA Mode)

The equivalent analog input circuit is shown in Figure 17. The

Capacitor C1 is typically 20 pF and can be attributed to pin

capacitance and 32 off-channels. When a channel is selected, an

extra 7.5 pF (typ) is switched in. This Capacitor C2 is charged

to the previously acquired voltage on that particular channel

so it must charge/discharge to the new level. It is essential that the

external source can charge/discharge this additional capaci-

tance within 1

acquired accurately. For this reason a low impedance source

is recommended.

C1

20pF

ADDRESSED CHANNEL

C2

7.5pF

Figure 17. Analog Input Circuit

Large source impedances will significantly affect the performance

of the ADC. This may necessitate the use of an input buffer

amplifier.

TRACK Function (SHA Mode)

Normally in SHA mode of operation,

TRACK is held high and

the channel begins to acquire when it is addressed. However, if

TRACK is low when the channel is addressed, V

the output buffer and an acquisition on the channel will not

occur until a rising edge of

TRACK. At this stage the BUSY pin

will go low until the acquisition is complete, at which point the

DAC assumes control of the voltage to the output buffer and